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15966 Commits

Author SHA1 Message Date
Akash Levy 2d771a352e Clean up Verific tests 2024-09-23 04:05:08 -07:00
Akash Levy 2c3d2b3ec6 Clocking works with -formal flag 2024-09-22 08:01:16 -07:00
Akash Levy 69bf7875dd Small edits 2024-09-22 07:52:58 -07:00
Akash Levy d655766c49 Smallfix 2024-09-22 06:57:28 -07:00
Akash Levy 89f9035a98 Fix VHDL checking 2024-09-22 06:45:47 -07:00
Akash Levy 7d5dac7255 More apt location for whereami 2024-09-22 06:02:20 -07:00
Akash Levy f1ab51ce5b Clean up and remove hdl_file_sort 2024-09-22 05:58:17 -07:00
Akash Levy facb9e8abe Disable plugins and slang for now 2024-09-22 05:24:23 -07:00
Akash Levy f0b1d2cac5 Small changes 2024-09-22 01:11:26 -07:00
Akash Levy 3b8c607dfd Update yosys-slang 2024-09-21 22:18:50 -07:00
Akash Levy 7f38ea8721 Update yosys-slang 2024-09-19 16:43:01 -07:00
Akash Levy 494eba8d66 Update yosys-slang 2024-09-19 16:36:30 -07:00
Martin Povišer 9018d06a33 quicklogic: Avoid carry chains in division mapping 
The default mapping rules for division-like operations (div/divfloor/
mod/modfloor) invoke subtractions which can get mapped to carry chains
in FPGA flows. Optimizations across carry chains are weak, so in
practice this ends up too costly compared to implementing the division
purely in soft logic.

For this reason arrange for `techmap.v` ignoring division operations
under `-D NODIV`, and use this mode in `synth_quicklogic` to avoid carry
chains for divisions.
 2024-09-19 12:18:47 +02:00
Akash Levy 4cf9bb86ca Smallfix 2024-09-19 01:04:29 -07:00
Akash Levy 7988a61f8c Use enable debug and switch order of Verific opt passes 2024-09-19 00:48:31 -07:00
Akash Levy 03f740e2a4 Undo annoying commit bdc43c6592 2024-09-18 22:05:23 -07:00
Akash Levy db0317afc5 Add support for int stuff 2024-09-18 16:46:53 -07:00
Akash Levy 1801bb966a Smallfix for slang support 2024-09-18 16:19:38 -07:00
Akash Levy c71203d5f9 Fix slang install dir 2024-09-18 16:15:51 -07:00
Akash Levy 2d139c8735 Smallfix to remove top/bottom-bound attributes 2024-09-18 14:46:13 -07:00
Martin Povišer f168b2f4b1 read_xaiger2: Update box handling 2024-09-18 16:55:02 +02:00
Martin Povišer 3a1b003cc3 celltypes: Fix `$buf` eval 2024-09-18 16:55:02 +02:00
Martin Povišer 5f8d7ff170 Start new write_xaiger2 backend for export w/ boxes 2024-09-18 16:55:02 +02:00
Martin Povišer ea765686b6 aiger2: Adjust hierarchy/port handling 2024-09-18 16:55:02 +02:00
Martin Povišer 2a3e907da8 aiger2: Adjust typing 2024-09-18 16:42:56 +02:00
Martin Povišer 72d65063c3 aiger2: Ignore benign cells 2024-09-18 16:42:56 +02:00
Martin Povišer 1ab7f29933 Start read_xaiger2 -sc_mapping 2024-09-18 16:42:56 +02:00
Martin Povišer 6cecf19ff4 aiger2: Ingest `$bmux` 2024-09-18 16:42:56 +02:00
Martin Povišer 1cfb9023c4 aiger2: Use `REDUCE` for reduction ops 2024-09-18 16:42:56 +02:00
Martin Povišer 6c1fa45995 aiger2: Ingest `$pmux` 2024-09-18 16:42:56 +02:00
Martin Povišer d5756eb9be tests: Add trivial liberty -unit_delay test 2024-09-18 16:17:03 +02:00
Martin Povišer 31476e89b6 tests: Avoid temporary script file 2024-09-18 16:17:03 +02:00
Martin Povišer 4976abb867 read_liberty: Optionally import unit delay arcs 2024-09-18 16:17:03 +02:00
Akash Levy a7b71684cc Updates 2024-09-17 22:43:23 -07:00
Akash Levy 9bb6daa43a
Merge branch 'YosysHQ:main' into main 2024-09-17 22:42:22 -07:00
github-actions[bot] 4d581a97d6 Bump version 2024-09-18 00:19:41 +00:00
Akash Levy 9f44ec8aa1
Merge branch 'YosysHQ:main' into main 2024-09-17 15:24:05 -07:00
Martin Povišer 9db1ca83fc aiger2: Drop `empty_lit()` as a function 2024-09-17 13:58:07 +02:00
Martin Povišer dbc937b2a7 aiger2: Describe supported cells in help 2024-09-17 13:55:58 +02:00
Martin Povišer e4b24e8200 aiger2: Fix literal typing 2024-09-17 13:55:58 +02:00
Martin Povišer 8e29675a23 aiger2: Support `$bwmux`, comparison operators 2024-09-17 13:55:58 +02:00
Martin Povišer d7128cb787 aiger2: Use shorthands 2024-09-17 13:55:58 +02:00
Martin Povišer e59387e5a9 aiger2: Add `aigsize` as a second user of index 2024-09-17 13:55:58 +02:00
Martin Povišer de8a2fb936 aiger2: Fix duplicate symbols on multibit ports 2024-09-17 13:55:58 +02:00
Martin Povišer 5671c10173 aiger2: Add strashing option 2024-09-17 13:55:58 +02:00
Martin Povišer fa39227416 aiger2: Support `$pos` 2024-09-17 13:55:58 +02:00
Martin Povišer fb26945a20 Start an 'aiger2' backend 2024-09-17 13:55:58 +02:00
Martin Povišer 4cfdb7ab50 Adjust operation naming in aigmap test 2024-09-17 13:55:58 +02:00
Martin Povišer a553b7c0c7
Merge pull request #3967 from YosysHQ/claire/bufnorm 
Add "buffered-normalized mode", add $buf cell type, and add "bufnorm" command
 2024-09-17 11:27:23 +02:00
Martin Povišer eeffca9470 simlib: Add `$buf` disclaimer 2024-09-17 10:46:20 +02:00