5 Commits

Author	SHA1	Message	Date
Lofty	b71f5bb908	synth_analogdevices: update timing model and tests	2026-02-20 10:57:46 +00:00
Krystine Sherwin	bdef403d92	analogdevices: Extra tests ... `mem_gen.py` based on quicklogic tests. Remove BUFG from `lutram.ys`. Extra `sync_ram_sp` models in `arch/common/blockram.v`. Add analogdevices to main makefile tests. Not all the other tests are passing, but that's fine for now.	2026-02-20 10:57:46 +00:00
Lofty	fa1c859d07	analogdevices: DSP inference	2026-02-20 10:57:46 +00:00
Krystine Sherwin	e7eae91abf	analogdevices: Update lutram.ys test	2026-02-20 10:57:45 +00:00
Lofty	bdf767e65e	test suite	2026-02-20 10:57:45 +00:00