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185 Commits

Author SHA1 Message Date
Mohamed Gaber dec28f65ae
Merge remote-tracking branch 'donn/pyosys_bugfixes' into merge_pybind11 2025-10-26 02:39:43 +03:00
Jannis Harder 6a0ee6e4fb Revert sim's cycle_width default back to 10, but keep -width option 2025-10-20 14:40:05 +02:00
Miodrag Milanovic f11a61b32b sim: Make cycle width small as possible and configurable 2025-10-16 11:37:44 +02:00
Akash Levy 60d969530b Bump to latest 2025-09-21 01:10:04 -07:00
Emil J 73e47ac3fe
Merge pull request #5357 from rocallahan/builtin-ff 
Instead of using `builtin_ff_cell_types()` directly, go through a method `Cell::is_builtin_ff()`
 2025-09-17 11:37:16 +02:00
Robert O'Callahan d24488d3a5 Instead of using builtin_ff_cell_types() directly, go through a method Cell::is_builtin_ff() 2025-09-17 03:24:19 +00:00
Robert O'Callahan a7c46f7b4a Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix() 2025-09-16 23:02:16 +00:00
Robert O'Callahan 5ac6858f26 Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
Robert O'Callahan d1642bf510 Update passes/sat to avoid bits() 2025-09-16 03:17:23 +00:00
Akash Levy f5cb0c328f Bump Yosys to latest 2025-09-13 04:35:52 -07:00
Robert O'Callahan e0ae7b7af4 Remove .c_str() calls from log()/log_error() 
There are some leftovers, but this is an easy regex-based approach that removes most of them.
 2025-09-11 20:59:37 +00:00
Akash Levy 1b3375d8df Merge upstream in 2025-09-09 05:50:48 -07:00
Robert O'Callahan c7df6954b9 Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00
Neil Deo 1122b92247 Use hardtabs 2025-08-08 11:08:20 -07:00
Neil Deo 07b54dff2b fix bad indentation 2025-08-08 10:39:25 -07:00
Neil Deo 88816e390e add clockgate to makefile, add Density to sim pass 2025-08-07 18:07:15 -07:00
Akash Levy 1f00bf0057 Bump yosys to latest 2025-05-15 14:44:26 -07:00
Krystine Sherwin d0b9a0cb98
sim.cc: Move cycle check 
Calling `throw dst_end_of_data_exception()` when the desired number of cycles has been reached means that the fst reader can't tidy up after itself and leads to memory leaks.
This doesn't happen when the `-stop` flag is used because the `Yosys::FstData` struct tracks the end time and skips the outer callback if the simulation has gone past the desired end time.
Move cycle checking into the inner callback along with the time checking means that the outer callback no longer needs to throw an exception in order to stop checking further values, while still allowing the fst reader to finish reading and deallocate memory.
 2025-05-12 12:48:01 +12:00
Krystine Sherwin cc402ee065
libs/fst: Update upstream 
libfst is no longer included in gtkwave and instead has its own repo.  There has also been some refactoring, so the patches need to update to match, as does sim.cc.
 2025-05-12 10:21:06 +12:00
Akash Levy aeed1ddb74 Update from upstream 2025-05-11 15:16:52 -07:00
Emil J. Tywoniak 90a2c92370 driver: allow --no-version still write things like Generated by Yosys 2025-05-07 11:34:23 +02:00
Akash Levy e241c9d513
Merge branch 'YosysHQ:main' into main 2025-04-10 14:28:10 -07:00
Krystine Sherwin cd3b914132
Reinstate #4768 
Revert the reversion so that we can fix the bugs that the PR missed.
 2025-04-08 11:58:05 +12:00
Akash Levy 06c614a010
Merge branch 'YosysHQ:main' into main 2025-04-07 07:28:06 -07:00
Miodrag Milanović d49364d96f
Revert "Refactor full_selection" 2025-04-07 12:11:55 +02:00
Akash Levy 0dab4308a3 Actual merge here 2025-04-06 18:53:43 -07:00
Akash Levy f218b5ba58 Revert "Represent memory size with size_t" 
This reverts commit bb5f8415af.
 2025-04-04 03:20:07 -07:00
Akash Levy bb5f8415af Represent memory size with size_t 2025-04-04 02:04:34 -07:00
Krystine Sherwin a3968d43f0
Drop deprecation on Design::selected_modules() 
Instead, change the default `Design::selected_modules()` to match the behaviour (i.e. `selected_unboxed_modules_warn()`) because it's a lot of files to touch and they don't really _need_ to be updated.
Also change `Design::selected_whole_modules()` users over to `Design::selected_unboxed_whole_modules()`, except `attrmap` because I'm not convinced it should be ignoring boxes.  So instead, leave the deprecation warning for that one use and come back to the pass another time.
 2025-03-14 14:08:56 +13:00
Akash Levy 1dcf75d175 Sync 2024-12-19 21:40:30 -08:00
Emil J. Tywoniak d071489ab1 hashlib: redo interface for flexibility 2024-12-18 14:49:25 +01:00
Alain Dargelas 88ff296657 Activity info and rename cmd 2024-12-11 11:04:35 -08:00
Akash Levy 2c5811daa1 Fix warnings 2024-12-09 11:45:09 -08:00
Alain Dargelas fe684f5fd2 Precision fix 2024-12-03 09:35:11 -08:00
Alain Dargelas f65d98a00d Simulation information for macro power 2024-12-02 20:15:53 -08:00
Alain Dargelas 5be70f436f Added stdout flush and statistical info for debug 2024-11-05 10:21:26 -08:00
Alain Dargelas 44fedf8186 Code cleanup 2024-10-23 09:33:06 -07:00
Alain Dargelas 2c506bfc1b Corrected activity and duty 2024-10-22 16:26:49 -07:00
Alain Dargelas c2aa611e5d Fix comments and add freq annotation in sim pass 2024-10-21 15:53:48 -07:00
Alain Dargelas 7e2c45b1e6 Large datastructures pass by ref in lambda capture 2024-10-17 19:48:10 -07:00
Alain Dargelas a54f450eb9 Fix coredump when wire is nullptr 2024-10-17 13:43:41 -07:00
Alain Dargelas f6d67ac21e More comments 2024-10-17 09:33:08 -07:00
Alain Dargelas 389518a8f0 tab issue 2024-10-16 21:37:41 -07:00
Alain Dargelas 516a4be6f8 Correct tab 2024-10-16 21:17:03 -07:00
Alain Dargelas 3f7c392e1a activity computation 2024-10-16 20:41:26 -07:00
Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Emily Schmidt bdb59ffc8e add -fst-noinit flag to sim for not initializing the state from the fst file 2024-08-21 11:03:29 +01:00
Miodrag Milanovic 6d98418f3d Set ranges on exported wires in VCD and FST 2024-08-02 15:23:00 +02:00
Jannis Harder 7c818d30f7 sim: Bring $print trigger/sampling semantics in line with FFs 2024-01-25 16:21:03 +01:00
Dag Lem acf916f654 Restore sim output from initial $display 2024-01-14 16:52:51 +01:00