6 Commits

Author	SHA1	Message	Date
Clifford Wolf	56432a920f	Added defparam support to Verilog/AST frontend	2013-07-04 14:12:33 +02:00
Clifford Wolf	0c6ffc4c65	More fixes for bugs found using xsthammer	2013-06-13 11:18:45 +02:00
Clifford Wolf	4b311b7b99	Further improved and extended xsthammer	2013-06-11 19:49:35 +02:00
Clifford Wolf	b56e06d2f5	Added support for verilog === operator	2013-05-07 14:35:40 +02:00
Clifford Wolf	7a99349de4	Improvements and bugfixes for generate blocks with local signals	2013-03-26 11:31:34 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00