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2642 Commits

Author SHA1 Message Date
nella a26e2adfe6
Merge 52b828e725 into 4821ed17b4 2026-07-29 09:48:58 +02:00
nella c1377426c9
Merge branch 'main' into nella/fuse-2 2026-07-29 01:41:37 +02:00
nella ab67fdd107 Test. 2026-07-27 16:27:45 +02:00
nella 42af67b8e7 Test. 2026-07-27 16:27:45 +02:00
Emil J 5d2fbf8187
Merge pull request #5961 from YosysHQ/emil/opt_muxtree-fix-reconvergence 
opt_muxtree: fix reconvergence
 2026-07-27 09:08:13 +00:00
nella 511017acc1
Merge branch 'main' into nella/fuse-2 2026-07-24 12:20:35 +02:00
nella 5e59deecc3 Fix test desc. 2026-07-24 12:07:10 +02:00
nella 7defa51862
Merge pull request #6007 from YosysHQ/nella/fix-shift-fold 
Fix wide shift count folded as truncated/signed negative count
 2026-07-24 08:17:11 +00:00
Krystine Sherwin 29a6295d7c
tests/opt: Fix comments 2026-07-23 14:59:12 +12:00
Miodrag Milanović bc14cd7d18
Merge pull request #6062 from YosysHQ/mmicko/tests_only 
Add dependencies to gtests
 2026-07-22 13:39:05 +00:00
Miodrag Milanovic 5574994453 Add dependencies to gtests 2026-07-22 15:03:12 +02:00
drewbabel 3006280d70
xilinx_srl: keep the clock enable on FDRE shift registers 
run_fixed inferred a fixed length shift register from a chain of FDRE
flops but assigned it ENPOL 2, which the cells_map template reads as no
enable and ties the enable high. FDRE has an active high clock enable, so
the shift register shifted every cycle and ignored stalls. Give FDRE and
FDRE_1 chains ENPOL 1 so the active high enable is kept.

Add tests/arch/xilinx/xilinx_srl_enable.ys covering the FDRE path.
 2026-07-20 23:59:40 -07:00
Miodrag Milanović e2c27aaafa
Merge pull request #6042 from YosysHQ/krys/symfpu 
Add `symfpu` pass
 2026-07-20 10:20:23 +00:00
Emil J 5f29546d80
Merge pull request #6050 from YosysHQ/emil/autoname-rewrite 
autoname: rewrite
 2026-07-19 22:10:02 +00:00
Emil J. Tywoniak 8565451ef9 autoname: selection determines what gets renamed, not the name it gets renamed to 2026-07-17 22:48:46 +02:00
Emil J. Tywoniak fb0bb160ad autoname: rewrite 2026-07-17 12:02:43 +02:00
Johan Olby 63457de80e
mul2dsp: normalize operand order 
Move the operand commute that puts the wider operand on A ahead of the
min-width checks. Checking the min-widths first made an asymmetric rule
(DSP_A_MINWIDTH != DSP_B_MINWIDTH) match only products that already had the
wider operand on A; a product in the other order was rejected before the
normalization.
 2026-07-15 16:21:07 +02:00
Krystine Sherwin 9dd5c3a6a4
symfpu: Run pre-commit 2026-07-15 14:56:11 +12:00
Krystine Sherwin e6bd07a49a
tests/symfpu: Switch to generate_mk.py 2026-07-15 14:50:33 +12:00
Krystine Sherwin 613d95b909
symfpu: Test comparisons 2026-07-15 14:50:30 +12:00
Krystine Sherwin 4134436a9f
tests/symfpu: Extra muladd tests 
Switch inputs back to `anyseq`, and add coverage for muladd with constant multiplier output and varying addend (also an assertion).
Use an `ifdef` to control clocked properties (because of the assertion, it's no longer just covers that are clocked).
 2026-07-15 14:50:29 +12:00
Krystine Sherwin b66c0dcc97
tests/symfpu: Testing sqrt 
Coverage supports `sqrt`, including new general rounding detection instead of just inf/ebmin/zero (since they aren't possible with `sqrt`).
More `sqrt` assertions, as well as the addition of `altsqrt` verification.
Some adjustments of macros.
 2026-07-15 14:50:29 +12:00
Krystine Sherwin db676a2eae
symfpu: Add altdiv 2026-07-15 14:50:28 +12:00
Krystine Sherwin 3f22dabb8d
tests/symfpu: Add cover checks 
Include mask/map for abc inputs (and switch to `anyconst` instead of `anyseq`).
Add false divide check for mantissa.
Covers aren't currently being tested by anything (and have to be removed for `sat`), but I've been using it locally with SBY to confirm that the different edge cases are able to be verified (e.g. when verifying HardFloat against symfpu while using the masked inputs to reduce solver time).
 2026-07-15 14:50:28 +12:00
Krystine Sherwin b818e1c8ca
Fix tininess when rounding to ebmin 2026-07-15 14:50:28 +12:00
Krystine Sherwin 5751023b6c
tests/symfpu: UF to ebmin is valid 2026-07-15 14:50:27 +12:00
Krystine Sherwin 70dad5a06e
Don't raise DZ when left is inf 2026-07-15 14:50:27 +12:00
Krystine Sherwin 717f7c5d3a
symfpu: Dynamic rounding mode 2026-07-15 14:50:27 +12:00
Krystine Sherwin 2dcaa944bf
symfpu: floatWithStatusFlags 
Now with verified muladd exceptions.
 2026-07-15 14:50:26 +12:00
Krystine Sherwin e44aeda246
symfpu: Verifying rounding modes 
Works for everything but muladd.
Which I saw coming, but am still frustrated by.
 2026-07-15 14:50:26 +12:00
Krystine Sherwin 2b39569477
symfpu: Configurable rounding modes 
Including tests, but currently only testing rounding modes on multiply.
Also missing the ...01 case.
 2026-07-15 14:50:25 +12:00
Krystine Sherwin 1347790f4d
symfpu: Add flags 
Use symfpu fork.
Add tests for symfpu properties and extra edge case checking for flags.
 2026-07-15 14:50:25 +12:00
Emil J. Tywoniak eb96123030 dfflibmap: add regression test for resetval clobber 2026-07-14 18:02:02 +02:00
nella dddf137888
Merge pull request #6024 from YosysHQ/nella/scl-build-date 
Include build datetime in scl cache hash
 2026-07-13 11:54:45 +00:00
nella ede98b81ac
Merge pull request #6023 from b-michi/michaelbaier/sc-649/segmentation-fault-during-proc-init-with 
Michaelbaier/sc 649/segmentation fault during proc init with
 2026-07-10 13:07:58 +00:00
nella eb93f5a066 Add scl caching test. 2026-07-10 14:52:06 +02:00
Michael Baier dca9234d86 Testcases for new truncation checks 2026-07-10 14:37:19 +02:00
Miodrag Milanovic f2f3f31646 Add initial codecov support 2026-07-10 12:19:59 +02:00
Michael Baier 086c50763d Tescases for Width Limit, Resize and Overflow 2026-07-09 14:34:56 +02:00
Michael Baier 3adb423e9e Added Testcase for bug1206 2026-07-09 14:34:56 +02:00
Lofty 75286287c6
Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7 
Move rename logic to abc_ops_reintegrate
 2026-07-09 08:46:46 +00:00
nella 8dc32cbf4e
Merge pull request #6012 from YosysHQ/nella/fix-opt-reduce 
`opt_reduce`: restore pmux b-slice == a elim
 2026-07-08 13:36:04 +00:00
nella f6d810acf9 Restore pmux elim. 2026-07-08 11:58:30 +02:00
nella f5809a7c2c
Merge branch 'main' into nella/latch-toggle 2026-07-08 11:41:08 +02:00
Miodrag Milanovic 8ad4ffcdd1 Cleanup 2026-07-08 08:34:01 +02:00
nella 5628dff0bd Fix wide shift count fold. 2026-07-07 15:04:57 +02:00
nella 8a2499b544
Merge pull request #5986 from YosysHQ/nella/x-wildcard 
fix case item containing x/z treated as wildcard in proc_rmdead
 2026-07-07 08:00:02 +00:00
Lofty 4e30b5c47b
Merge pull request #5997 from mole99/leo/fabulous-updates 
FABulous Updates
 2026-07-07 06:35:32 +00:00
nella 310016a812 Rm. 2026-07-07 04:03:17 +02:00
nella 006cbc8f72
Merge pull request #5842 from YosysHQ/nella/opt_dff_elim_improvements 
opt_dff: Eliminate equivalent bits
 2026-07-06 12:02:50 +00:00