luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-04 19:31:00 +02:00
Code Issues Packages Projects Releases Wiki Activity
15,401 Commits 156 Branches 70 Tags
a18acaca82e304e5e6ddc4fbf21b0abdf0b40fa6
Commit Graph
1 Commits
Author SHA1 Message Date
Udi Finkelstein 536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
 2018-10-25 02:37:56 +03:00