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4932 Commits

Author SHA1 Message Date
Emil J. Tywoniak 80baffb60e flatten: redo signormalization to work around fanout issue 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak e75523bf61 signorm: disable passes that use rewrite_sigspecs 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak 99f88aa7e8 check: stitch info about $connect ports together for driver analysis 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak d001b407c4 abstract: skip $input_port cells 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak e7bffe1d75 flatten: skip $input_port cells in template module 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak e8dd4868c1 signorm: disable in passes that use swap_names 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak 0c9d373458 opt_expr: fix invert_map 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak 1da5f4dfef techmap: disable signorm more 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak 9d98604020 techmap: disable signorm 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak d37e0acc1f opt_hier: disable signorm 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak 6defcfab50 opt_merge_inc: re add initvals deletion 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak 42a75ffda9 wreduce: fixup initvals after setPort 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak d8520e20bc check: don't fail on $input_port 2026-05-05 21:35:13 +02:00
Jannis Harder 7a6c111375 WIP half broken snapshot 2026-05-05 21:35:13 +02:00
Emil J 627b691578
Merge pull request #5831 from stashcroft/main 
Make sure co-simulation only uses integer arithmetic
 2026-04-27 14:03:58 +00:00
Emil J 30a914167f
Merge pull request #5809 from QuantamHD/pmux_on2 
opt: Remove O(n²) opt routines across the codebase for pmux
 2026-04-24 19:03:40 +00:00
Emil J. Tywoniak e0b833ac1a opt_muxtree: dense knowledge 2026-04-24 11:07:58 +02:00
Emil J. Tywoniak 4abaca273e opt_reduce: further optimization 2026-04-24 11:07:58 +02:00
Scott Ashcroft 23a05fcf35 Add comments to make sure it is clear scale is an exponent of 10 2026-04-23 17:22:14 +01:00
Scott Ashcroft e69341cd5f Make sure co-simulation only uses integer arithmetic 2026-04-23 17:22:14 +01:00
nella d795a4f1d2 Fix WASI, store in temp dir. 2026-04-23 12:43:43 +02:00
nella afac9a28b0 Fix WASI build. 2026-04-23 12:43:43 +02:00
nella 5d4d94a5dd Fix mac compile. 2026-04-23 12:43:43 +02:00
nella 94a215b4f7 Add dont_use_cells to scl cache. 2026-04-23 12:43:43 +02:00
nella edd3ad525e Add scl caching to abc_new. 2026-04-23 12:43:43 +02:00
nella 9143178343 Merge liberty files into stripped scl files. 2026-04-23 12:43:43 +02:00
N. Engelhardt 240f7030b2 xprop: ignore $scopeinfo cells 2026-04-21 10:52:50 +02:00
Emil J. Tywoniak b4c081c70b abc: fix deferred logs 2026-04-17 13:35:47 +02:00
nella 4506dffa9f Fix use after free. 2026-04-13 12:48:05 +02:00
nella fc71719e6e Rename csa_tree to arith_tree. 2026-04-13 12:48:05 +02:00
nella c3c577f333 Fix test cases. 2026-04-13 12:48:05 +02:00
nella 135812ab02 Further CSA cleanup. 2026-04-13 12:48:05 +02:00
nella 847a8941e9 Clang-Format CSA tree. 2026-04-13 12:48:05 +02:00
nella a02c238874 Consolidate Wallace from booth and CSA. 2026-04-13 12:48:05 +02:00
nella 4bbffecf98 Invert. 2026-04-13 12:48:05 +02:00
nella 42c309347b Clarify. 2026-04-13 12:48:05 +02:00
Emil J. Tywoniak b6d656e932 csa_tree: move to techmap 2026-04-13 12:48:05 +02:00
Emil J. Tywoniak b6a8feec22 csa_tree: refactor 2026-04-13 12:48:05 +02:00
nella 67e145618b Replace utf arrow with ascii arrow. 2026-04-13 12:48:05 +02:00
nella 5d90bcc792 CSA add support for macc and alu cells. 2026-04-13 12:48:05 +02:00
nella 335cce4895 Add sub chain support for csa trees. 2026-04-13 12:48:05 +02:00
nella e69914b8be better balancing. 2026-04-13 12:48:05 +02:00
nella 46df888191 impl csa tree. 2026-04-13 12:48:05 +02:00
Lofty 564c617721
Merge pull request #5790 from Eiko-Eira/main 
Fixed typos and incorrect grammar
 2026-04-11 03:26:55 +00:00
Emil J 86448c0001
Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef 
Undefine set&reset behavior of $dffsr
 2026-04-08 14:22:34 +00:00
Emil J. Tywoniak 41b69df2cb abc_new: stable TopoSort 2026-04-06 15:09:52 +02:00
Noah Van Dijk 52243e10fb
Fix typo in pmgen/README.md 
Line 161:
calulated > calculated
 2026-04-02 10:24:31 -05:00
Emil J cede13a742
Merge pull request #5765 from YosysHQ/emil/muxpack-wide-port 
muxpack: fix wide Y port handling
 2026-03-31 10:49:39 +00:00
tondapusili 5b22e64d19 sim: cache sigmap in register_output_step_values 2026-03-24 16:10:11 -07:00
Miodrag Milanović 66306a8ca3
Merge pull request #5769 from Silimate/optimize_sim_pass 
sim: early return from checkSignals in sim mode
 2026-03-23 17:19:26 +00:00