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807 Commits

Author SHA1 Message Date
Greeshma Manjegowda 8c7b1921d2 ast: guard against module name collision during reprocessing 
process_module() could hit the modules_.count(module->name) == 0
assertion in Design::add() when a module gets reprocessed via
AstModule::reprocess_if_necessary(). This happens for a
parameterized module that instantiates a submodule inside a
generate block, where the submodule only becomes available after
the enclosing module's initial derivation. In that case,
process_module() could attempt to register a module under a name
that was already occupied.

Guard the design add call in process_module() by removing any
stale module already registered under the target name before
adding the newly generated one.

Verified against the reproduction case in issue #6002 (multiply
elaborates successfully without crashing) and confirmed the
previously working divide case produces identical output before
and after this change.

Fixes #6002
 2026-07-24 17:30:01 -05:00
Miodrag Milanovic 48a3dcc02a End of file fix 2026-06-23 07:23:41 +02:00
nella 5d7486115a
Merge pull request #5887 from YosysHQ/nella/fix-signedness-4402 
Fix: `read_verilog` doesn't respect `signed` keyword
 2026-06-18 16:53:37 +00:00
Krystine Sherwin b79c7c008d
simplify.cc: Fix crash when identifier matches module 
Also update one of the AST debug prints that is guarded by an `#if 0` but was out of date.
 2026-06-12 11:54:53 +12:00
Miodrag Milanovic 102f008194 Remove EMSCRIPTEN leftovers 2026-06-05 10:03:27 +02:00
Catherine a727e7f6e7 Migrate build system to CMake 
See #5895 for details.

This commit does not include CI or documentation changes.
 2026-06-03 08:58:10 +00:00
Emil J. Tywoniak 80bdbaa010 genrtlil: don't avoid emitting flops for nosync 2026-05-29 11:37:08 +02:00
Miodrag Milanovic 4a7878b17f Fixing couple more conversion errors 2026-05-14 15:58:58 +02:00
Miodrag Milanovic 9580ebabc5 log_id here was needed for unescaping 2026-05-14 12:35:01 +02:00
nella 38c2806636 Make sure to apply correct signedness to loop vars. 2026-05-13 16:52:07 +02:00
Codexplorer e41b969da2 Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
Christopher D. Leary 390f09b89a Support positional assignment patterns for unpacked arrays 2026-04-23 14:29:38 -07:00
Petter Reinholdtsen a89e8fd869 Fixed spelling error in message of frontends/ast/genrtlil.cc. 
Patch by Ruben Undheim via the Debian project.  The patch originated
as 0009-Some-spelling-errors-fixed.patch and was dated 2018-07-12
there.

See also issue #5805.
 2026-04-22 04:30:18 +02:00
Emil J. Tywoniak ad7a776d73 genrtlil: even faster removeSignalFromCaseTree 2026-03-18 23:33:35 +01:00
Emil J. Tywoniak 23ce4b8560 genrtlil: faster removeSignalFromCaseTree 2026-03-18 23:33:35 +01:00
Emil J 629bf3dffd
Merge pull request #5630 from apullin/array-assignment 
ast: Add support for array-to-array assignment
 2026-03-05 11:10:12 +00:00
Andrew Pullin 6ac8c8cb05 ast: Add support for array-to-array assignment 
This commit adds support for SystemVerilog array-to-array assignment
operations that were previously unsupported:

1. Direct array assignment: `b = a;`
2. Array ternary expressions: `out = sel ? a : b;`

Both single-dimensional and multi-dimensional unpacked arrays are
supported. The implementation expands these array operations during
AST simplification into element-wise assignments.

Example of now-supported syntax:
```systemverilog
wire [7:0] state_regs[8];
wire [7:0] r[8];
wire [7:0] sel[8];
assign sel = condition ? state_regs : r;
```

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
 2026-03-04 21:34:40 -08:00
likeamahoney e9442194f2 support automatic lifetime qualifier on procedural variables 2026-02-27 20:42:52 +03:00
Martin Povišer f67d4bcfa4 verilog: Do not set `module_not_derived` on internal cells 2026-01-19 16:48:13 -08:00
Emil J 5ba0e9cae3
Merge pull request #4235 from ylm/genblk_wire 
Add autowires in genblk/for expension
 2026-01-13 16:40:22 +01:00
N. Engelhardt d5b38af4a7
Merge pull request #5550 from YosysHQ/nak/dont_merge_properties 2025-12-22 16:54:43 +01:00
Robert O'Callahan 46cb05c471 Pass IdString by value instead of by const reference. 
When IdString refcounting was expensive, it made sense to pass it by const reference
instead of by value, to avoid refcount churn. Now that IdString is not refcounted,
it's slightly more efficient to pass it by value.
 2025-12-22 01:52:59 +00:00
N. Engelhardt 45d654e2d7 avoid merging formal properties 2025-12-17 20:25:24 +01:00
Yannick Lamarre 9814f9dc4f Add autowires in genblk/for expension 
Signed-off-by: Yannick Lamarre <yan.lamarre@gmail.com>
 2025-12-10 14:43:42 +01:00
KrystalDelusion 529886f7fb
Merge pull request #5473 from YosysHQ/krys/unsized_params 
Handle unsized params
 2025-11-12 07:14:44 +13:00
Emil J. Tywoniak 8f53d21ea7 simplify: refactor specific package import 2025-11-10 14:26:10 +01:00
Rahul Bhagwat 224109151d
add specific package imports and tests 2025-11-08 23:05:10 +05:30
Krystine Sherwin 7302bf9a66
Add CONST_FLAG_UNSIZED 
In order to support unsized constants being used as parameters, the `const` struct needs to know if it is unsized (so that the parameter can be used to set the size).
Add unsized flag to param value serialization and rtlil back-/front-end.
Add cell params to `tests/rtlil/everything.v`.
 2025-11-07 17:45:07 +13:00
Krystine Sherwin a5cc905184
simplify.cc: Fix unsized const in params 2025-11-07 15:52:24 +13:00
Emil J. Tywoniak 5cfe6a9c1e reduce OS ifdefs, refactor getting dirs and filenames from paths to files 2025-10-14 15:46:17 +02:00
Jannis Harder 79e05a195d verilog: Bufnorm cell backend and frontend support 
This makes the Verilog backend handle the $connect and $input_port
cells. This represents the undirected $connect cell using the `tran`
primitive, so we also extend the frontend to support this.
 2025-09-17 14:01:09 +02:00
Robert O'Callahan a1141f1a4c Remove some unnecessary .c_str() calls to the result of unescape_id() 2025-09-16 23:12:14 +00:00
Robert O'Callahan d276529d46 Remove .c_str() calls from parameters to log_file_info() 2025-09-16 23:06:28 +00:00
Robert O'Callahan 548deba259 Remove .c_str() calls from parameters to log_file_warning() 2025-09-16 23:03:45 +00:00
Robert O'Callahan a7c46f7b4a Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix() 2025-09-16 23:02:16 +00:00
Robert O'Callahan d1fd6de6da Remove .c_str() calls from parameters to log_header() 2025-09-16 23:00:42 +00:00
Robert O'Callahan 5ac6858f26 Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
Robert O'Callahan f65ca488ec Update frontends to avoid bits() 2025-09-16 03:17:23 +00:00
Jannis Harder 193b057983
Merge pull request #5341 from rocallahan/more-varargs-conversion 
More varargs conversion
 2025-09-12 18:09:42 +02:00
Robert O'Callahan 733b6f0124 Remove unnecessary usage of .c_str() in parameters to input_error() 2025-09-12 06:03:05 +00:00
Robert O'Callahan ad4ef8b775 Make AstNode::input_error use C++ stringf machinery 2025-09-12 06:01:32 +00:00
Robert O'Callahan e0ae7b7af4 Remove .c_str() calls from log()/log_error() 
There are some leftovers, but this is an easy regex-based approach that removes most of them.
 2025-09-11 20:59:37 +00:00
Robert O'Callahan c7df6954b9 Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00
Emil J. Tywoniak 8582136a45 simplify: fix $initstate segfault 2025-08-12 12:39:36 +02:00
Emil J. Tywoniak 99ab73424d verilog_location: rename location to Location to avoid conflict with Pass::location 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 5195f81257 ast: fix import node 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 740ed3fc1c ast: refactor 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 646c45e6b8 ast: remove null_check as dead code 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 25d2a8ce3a simplify: simplify 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 97bc0088d8 simplify: std::gcd 2025-08-11 13:34:10 +02:00