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1403 Commits

Author SHA1 Message Date
Akash Levy 4356eae4c9 Yosys sync 2024-12-04 14:16:55 -08:00
Martin Povišer 14ee5ce800
Merge pull request #4787 from povik/booth-macc 
booth: Map simple `$macc` instances too
 2024-12-04 11:49:34 +01:00
Emil J 3b8e8ee012
Merge pull request #4797 from YosysHQ/emil/multiple-liberty 
Allow multiple -liberty args in dfflibmap and clockgate
 2024-12-04 11:18:52 +01:00
Martin Povišer 384c191192
Merge pull request #4775 from povik/dont_map 
techmap: Add `-dont_map` for selective disabling of rules
 2024-12-03 20:21:47 +01:00
Martin Povišer 1c7bb700c9 techmap: Rephrase help 2024-12-03 20:20:00 +01:00
Emil J. Tywoniak 6edf9c86cb libparse: add LibertyMergedCells, enable multiple -liberty args for dfflibmap and clockgate 2024-12-03 17:36:00 +01:00
Emil J. Tywoniak 60fb241cb3 clockgate: clean up argument parsing 2024-12-03 17:35:10 +01:00
Akash Levy e0cef06b52
Merge branch 'YosysHQ:main' into main 2024-12-02 19:39:14 -05:00
KrystalDelusion 889894a6d2
Merge pull request #4790 from YosysHQ/emil/clockgate-warnings 
clockgate: reduce build warnings
 2024-12-03 13:25:52 +13:00
Lofty fd05f73d50 dfflibmap: demote some warnings to debug 2024-12-02 14:17:51 +00:00
Emil J. Tywoniak 6b006e5f61 clockgate: reduce build warnings 2024-12-02 10:07:01 +01:00
Martin Povišer 1ded817beb booth: Map simple `$macc` instances too 2024-12-01 16:00:04 +01:00
Martin Povišer 2962f8fa88 techmap: Add `-dont_map` for selective disabling of rules 2024-11-27 15:54:37 +01:00
Alain Dargelas e9b7db0a4a Selective boolopt 2024-11-25 15:22:16 -08:00
Alain Dargelas b2587f5e68 Selective boolopt 2024-11-25 15:19:35 -08:00
Alain Dargelas e8e25b4cea Selective boolopt 2024-11-25 15:18:22 -08:00
Alain Dargelas 10bad88bdb Selective boolopt 2024-11-25 15:15:35 -08:00
Alain Dargelas 13915dee96 Selective boolopt 2024-11-25 15:14:14 -08:00
Alain Dargelas c32d0a412c Selective boolopt 2024-11-25 15:08:42 -08:00
Akash Levy 52a1493548 Naming improvements 2024-11-21 03:29:35 -08:00
Akash Levy f855b39dbb
Merge branch 'YosysHQ:main' into main 2024-11-21 00:34:49 -08:00
Akash Levy b9456acdd1 Remove unused and_cell 2024-11-20 20:36:39 -08:00
Emil J. Tywoniak 4d96cbec75 clockgate: reduce errors to warnings 2024-11-18 18:32:18 +01:00
Emil J. Tywoniak 983c54c75f clockgate: help string add -dont_use and -liberty 2024-11-18 13:57:49 +01:00
Emil J. Tywoniak a5bc36f77e clockgate: add -dont_use 2024-11-18 13:45:30 +01:00
Emil J. Tywoniak e6793da9a0 clockgate: refactor 2024-11-18 12:50:25 +01:00
Akash Levy 0e00fc9824 Add breaksop 2024-11-16 21:58:17 -08:00
Akash Levy aad94abef4 aigmap fix prefix 2024-11-16 21:58:11 -08:00
Akash Levy 6be73e5c2e Updates 2024-11-15 19:02:06 -08:00
Emil J. Tywoniak 45880ea7f2 clockgate: add -liberty 2024-11-14 20:37:59 +01:00
Lofty 4f40187759 dfflibmap: move expression code into libparse 2024-11-13 16:06:57 +00:00
Lofty 08ed2c765e dfflibmap: enable inference 2024-11-13 15:57:45 +00:00
Martin Povišer 9da7341003
Merge pull request #4727 from georgerennie/george/bufnorm_constants2 
bufnorm: preserve constant bits when mapping back to connections
 2024-11-13 14:32:15 +01:00
Akash Levy e99828dc94 Add aigmap 2024-11-12 12:00:09 -08:00
Akash Levy 894c9816d3 Improve naming: big fix 2024-11-11 17:06:11 -08:00
Emil J. Tywoniak 49e1597ea4 filterlib: preserve value quotes 2024-11-12 01:21:07 +01:00
George Rennie ff6c9446c0 bufnorm: preserve constant bits when mapping back to connections 2024-11-12 01:05:15 +01:00
Akash Levy 0e3adb38fc
Merge branch 'YosysHQ:main' into main 2024-11-07 11:24:11 -08:00
George Rennie 8f6058a7d6 bufnorm: preserve constant bits driving wires 2024-11-07 11:48:48 +01:00
Akash Levy c2f95d1b5a Add more Liberty tests and fix parentheses in functions 2024-11-05 10:34:51 -08:00
Akash Levy 72f511ae29 Updates to bmuxmapping and selectconst 2024-11-05 01:00:12 -08:00
Akash Levy 1cba744712 Update 2024-11-04 17:01:41 -08:00
Akash Levy 1eb577120e Bmux unq 2024-11-04 12:03:53 -08:00
Martin Povišer cbe73c9047 cellmatch: Visit whiteboxes for `-derive_luts` 2024-11-04 14:28:46 +01:00
Martin Povišer c9ed6d8dcf cellmatch: Rename `-lut_attrs` to `-derive_luts`; document option 2024-11-04 14:28:40 +01:00
Akash Levy a2ea3c1e7a Fix colon issue 2024-11-01 17:49:29 -07:00
Akash Levy b4d7812662 Add abc, some techmap passes, make opt_balance_tree only balance add/mul 2024-10-30 00:38:05 -07:00
Akash Levy 469f5a707a
Merge branch 'YosysHQ:main' into main 2024-10-14 11:21:54 -07:00
Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Akash Levy bf4b7ec0ea
Merge branch 'YosysHQ:main' into main 2024-10-11 15:40:49 -07:00