13 Commits

Author	SHA1	Message	Date
Marcin Kościelnicki	666c6128a9	xilinx_dsp: Initial DSP48A/DSP48A1 support.	2019-12-22 20:51:14 +01:00
Marcin Kościelnicki	15232a48af	Fix #1462, #1480.	2019-11-19 08:57:39 +01:00
Eddie Hung	f90a4b1e24	Missed this	2019-10-05 08:57:37 -07:00
Eddie Hung	991c2ca95b	Add comment on why we have to match for clock-enable/reset muxes	2019-10-05 08:56:37 -07:00
Eddie Hung	12fd2ec4f0	Improve comments for xilinx_dsp_CREG	2019-10-04 22:31:04 -07:00
Eddie Hung	77d7a5c14a	Retry on fixing TODOs	2019-10-04 22:31:04 -07:00
Eddie Hung	52583ecff8	Revert "Fix TODOs" ... This reverts commit 8674a6c68d563908014d16671567459499c6dc99.	2019-10-04 22:31:04 -07:00
Eddie Hung	6d68972619	More comments, cleanup	2019-10-04 22:31:04 -07:00
Eddie Hung	7de9c33931	Fix TODOs	2019-10-04 22:31:04 -07:00
Eddie Hung	983068103e	Consistency	2019-10-04 22:31:04 -07:00
Eddie Hung	cf82b38478	Add comments for xilinx_dsp	2019-10-04 22:31:04 -07:00
Eddie Hung	bd8661e024	CREG to check for \keep	2019-09-26 10:32:01 -07:00
Eddie Hung	15dfbc8125	Separate out CREG packing into new pattern, to avoid conflict with PREG	2019-09-23 13:27:10 -07:00