5 Commits

Author	SHA1	Message	Date
Eddie Hung	fdafb74eb7	kernel: use more ID::*	2020-04-02 07:14:08 -07:00
Eddie Hung	4555b5b819	kernel: more pass by const ref, more speedups	2020-03-18 11:21:53 -07:00
Miodrag Milanovic	c0b14cfea7	Fixes for MSVC build	2019-10-04 16:29:46 +02:00
Miodrag Milanovic	c026579c20	Define environ, fixes #1424	2019-10-01 18:45:07 +02:00
whitequark	99a7f39084	rpc: new frontend. ... A new pass, connect_rpc, allows any HDL frontend that can read/write JSON from/to stdin/stdout or an unix socket or a named pipe to participate in elaboration as a first class citizen, such that any other HDL supported by Yosys directly or indirectly can transparently instantiate modules handled by this frontend. Recognizing that many HDL frontends emit Verilog, it allows the RPC frontend to direct Yosys to process the result of instantiation via any built-in Yosys frontend. The resulting RTLIL is then hygienically integrated into the overall design.	2019-09-30 15:53:11 +00:00