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150 Commits

Author SHA1 Message Date
Emil J. Tywoniak 547a715659 tests: adjust to input_port and init behavior (sketchy) 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak 66f2d67f5e tests: adjust to input_port and init behavior (sketchy) 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak 0673455daa tests: adjust to input_port and init behavior (sketchy) 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak 92f97bd5e7 tests: adjust to input_port and init behavior (sketchy) 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak 57ee22883a bug2920: disable 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak 3faa9b46de tests: adjust to input_port and init behavior (sketchy) 2026-05-05 21:35:13 +02:00
Miodrag Milanovic ced2521b03 Convert gen-tests shell script to python 2026-04-16 11:00:44 +02:00
Robert O'Callahan 7f3b11e56b Add test that connects a wire with `init` to a constant 2026-03-06 02:20:08 +00:00
Emil J 5f8489d36d
Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors 
equiv_induct: error on missing model
 2026-02-25 15:39:31 +01:00
Emil J. Tywoniak 2efd0247a1 opt_hier: fix test 2026-02-03 18:10:29 +01:00
Emil J. Tywoniak 3bfeaee8ca opt_expr: fix const lhs of $pow to $shl 2026-02-03 11:59:00 +01:00
Robert O'Callahan 32e96605d4 Don't update `used_signals` for retained wires in `rmunused_module_signals`. 
These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.

These updates will also make it difficult to process these wires in parallel.
 2026-01-24 03:41:18 +00:00
Natalia d5e1647d11 fix tests with truncation issues 2026-01-14 18:03:30 -08:00
Natalia Kokoromyti 8b6925c5b0 Add opt_balance_tree pass for timing optimization 
This pass converts cascaded chains of arithmetic and logic cells ($add,
$mul, $and, $or, $xor) into balanced binary trees to improve timing
performance in hardware synthesis.

The optimization uses a breadth-first search approach to identify chains
of compatible cells, then recursively constructs balanced trees that
reduce the critical path depth.

Features:
- Supports arithmetic cells: $add, $mul
- Supports logic cells: $and, $or, $xor
- Command-line options: -arith (arithmetic only), -logic (logic only)
- Preserves signed/unsigned semantics
- Comprehensive test suite with 30 test cases

Original implementation by Akash Levy <akash@silimate.com> for Silimate.
Upstreamed from https://github.com/Silimate/yosys
 2026-01-13 14:20:11 -08:00
Emil J 2e1a2cfacb
Merge pull request #5561 from YosysHQ/emil/opt_expr-test-avoid-multiple-drivers 
opt_expr: avoid multiple drivers in test
 2026-01-06 14:54:55 +01:00
Emil J. Tywoniak 856d455065 opt_expr: avoid multiple drivers issue #4792 in combined assign tests 2025-12-19 18:32:56 +01:00
Emil J. Tywoniak 772d821fb0 opt_expr: reindent test 2025-12-19 18:32:56 +01:00
N. Engelhardt 45d654e2d7 avoid merging formal properties 2025-12-17 20:25:24 +01:00
Miodrag Milanović 4cdaac003f
Merge pull request #3991 from adrianparvino/alumacc-sign 
alumacc: merge independent of sign
 2025-10-08 13:02:10 +02:00
Martin Povišer ffe2f7a16d opt_hier: Fix two optimizations conflicting 
Fix a conflict between the following two:

 * propagation of tied-together inputs in
 * propagation of unused inputs out
 2025-09-29 12:27:27 +02:00
Emil J. Tywoniak 8333a83cef opt_dff: more explicit testing, typo 2025-08-27 11:29:57 +02:00
Anhijkt e1276560cd opt_dff: add another test 2025-08-19 23:48:45 +03:00
Anhijkt e486994f60 opt_dff: add test 2025-08-14 00:13:23 +03:00
Robert O'Callahan 8b75c06141 Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
Martin Povišer 22a44e4333 Start `opt_hier` 2025-07-05 16:45:52 +02:00
George Rennie 7160c91800 tests: add test for #5164 opt_dff -sat UAF 2025-06-06 23:46:23 +01:00
George Rennie 353fd0f7f4 tests: test opt_expr for 32 bit unsigned shifts 2025-05-26 15:28:44 +01:00
George Rennie d59380b3a0 tests: more complete testing of shift edgecases 2025-05-08 11:09:01 +02:00
George Rennie af933b4f38 tests: check shifts by amounts that overflow int 2025-05-07 15:12:33 +02:00
George Rennie 70a44f035c tests: test opt_expr constant shift edge cases 2025-04-26 12:40:04 +02:00
Krystine Sherwin 406b400458
opt_expr: Fix #4590 
If all the (non-select) inputs of a `$_MUX{4,8,16}_` are undefined, replace it, just like we do for `$mux` and `$_MUX_`.
Add `tests/opt/opt_expr_mux_undef.ys` to verify this.

This doesn't do any const folding on the wide muxes, or shrinking to less wide muxes.  It only handles the case where all inputs are 'x and the mux can be completely removed.
 2025-04-04 12:25:31 +13:00
George Rennie 63b3ce0c77
Merge pull request #4971 from Anhijkt/pow-optimization 
opt_expr: optimize pow of 2 cells
 2025-04-03 14:34:36 +02:00
Anhijkt c57cbfa8f9 opt_expr: add test 2025-04-01 21:54:46 +03:00
Emil J 3a1255546a
Merge pull request #4975 from YosysHQ/emil/opt_expr-cover-with-tests 
opt_expr: expand test coverage
 2025-03-31 20:13:16 +02:00
Emil J. Tywoniak 6194eb939d opt_expr: expand test coverage 2025-03-31 19:31:53 +02:00
Emil J. Tywoniak 33bfc9d19c opt_merge: test more kinds of cells 2025-03-10 13:14:06 +01:00
Emil J. Tywoniak ae7a97cc2d opt_merge: test some unary cells 2025-03-10 13:14:06 +01:00
Emil J. Tywoniak 176faae7c9 opt_merge: fix trivial binary regression 2025-03-10 13:14:06 +01:00
Krystine Sherwin db5b76edc1
Add test for shifting by INT_MAX 
Currently resulting in CI failing on main during fsm checks which generate a circuit that simplifies to this.
 2025-02-14 14:01:27 +13:00
Emil J. Tywoniak 6240aec433 test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
George Rennie 9043dc0ad6
tests: replace read_ilang with read_rtlil 
* #4612 was written before read_ilang was deprecated but merged after so caused test failures. This switches read_ilang to read_rtlil
 2024-11-20 14:54:23 +01:00
Emil J cc17d5bb70
Merge pull request #4612 from georgerennie/george/opt_demorgan_zero_width 
opt_demorgan: skip zero width cells
 2024-11-20 13:33:16 +01:00
Emil J 18459b4b09
Merge pull request #4614 from georgerennie/george/opt_reduce_cell_width 
opt_reduce: keep at least one input to $reduce_or/and cells
 2024-11-20 13:33:04 +01:00
Krystine Sherwin ee73a91f44
Remove references to ilang 2024-11-05 12:36:31 +13:00
George Rennie 0572f8806f opt_reduce: add test for constant $reduce_and/or not being zero width 2024-09-25 16:28:41 +01:00
George Rennie e105cae4a9 opt_demorgan: add test for zero width cell 2024-09-25 16:10:16 +01:00
phsauter 34b5c6d062 peepopt: avoid shift-amount underflow 2024-06-13 23:30:07 +02:00
Martin Povišer 5924d97381 tests: Remove part of test involving combinational loops 2024-03-11 10:45:36 +01:00
Adrian Parvin Ouano 062dbf2c96 alumacc: add signed-independent comparison tests 2023-10-09 00:36:22 +08:00
Charlotte d130f7fca2 tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00