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2079 Commits

Author SHA1 Message Date
Emil J. Tywoniak 8f53d21ea7 simplify: refactor specific package import 2025-11-10 14:26:10 +01:00
Rahul Bhagwat 54e5eb1c3c
no use vector 2025-11-08 23:16:52 +05:30
Rahul Bhagwat 224109151d
add specific package imports and tests 2025-11-08 23:05:10 +05:30
Krystine Sherwin 7302bf9a66
Add CONST_FLAG_UNSIZED 
In order to support unsized constants being used as parameters, the `const` struct needs to know if it is unsized (so that the parameter can be used to set the size).
Add unsized flag to param value serialization and rtlil back-/front-end.
Add cell params to `tests/rtlil/everything.v`.
 2025-11-07 17:45:07 +13:00
Krystine Sherwin a5cc905184
simplify.cc: Fix unsized const in params 2025-11-07 15:52:24 +13:00
KrystalDelusion 52c108cd6a
Merge pull request #4596 from YosysHQ/emil/path-sep-refactor 
Refactor getting dirs and filenames from paths to files
 2025-11-05 09:12:54 +13:00
Robert O'Callahan 25aafab86b Set `port_id` for Verific PortBus wires 2025-10-23 20:51:53 +00:00
Emil J 9d21585a4c
Merge pull request #5426 from rocallahan/parse-sigspec 
Don't stop parsing sigspec after a {} group.
 2025-10-15 17:31:11 +02:00
Robert O'Callahan e099a7d34a Don't stop parsing sigspec after a {} group. 
Resolves #5424
 2025-10-14 21:18:58 +00:00
Emil J. Tywoniak 5cfe6a9c1e reduce OS ifdefs, refactor getting dirs and filenames from paths to files 2025-10-14 15:46:17 +02:00
Miodrag Milanovic 1f11b2c529 verific: Add src to message missed in #5406 2025-10-13 15:16:17 +02:00
Miodrag Milanovic dc959cdf4a verific: Fix error compiling without VERIFIC_LINEFILE_INCLUDES_COLUMNS 2025-10-13 15:16:17 +02:00
Miodrag Milanovic 9570b39519 verifix: fix bits() deprecation warnings 2025-10-13 09:57:22 +02:00
Miodrag Milanovic 2f8f421dee verifix: fix bits() deprecation warnings 2025-10-13 09:47:18 +02:00
Emil J a80462f27f
Merge pull request #5339 from rocallahan/fast-rtlil-parser 
Rewrite the RTLIL parser for efficiency
 2025-10-08 14:52:37 +02:00
N. Engelhardt 0b6adf832b verific: print source location of problematic object on import error (if available) 2025-10-03 12:57:49 +02:00
Robert O'Callahan 915ad949f9 Limit the maximum size of parsed RTLIL constants to 1 Gb. 
Without this check it's trivially easy to crash Yosys with a tiny RTLIL input
by specifying a constant with very large width. Fuzz testers love hitting this
over and over again.
 2025-10-01 02:17:22 +00:00
Robert O'Callahan ac4cb5e460 Implement a handwritten recursive-descent RTLIL parser with minimal copying 2025-10-01 02:17:22 +00:00
ShinyKate 30cb72a162
Merge pull request #4125 from povik/read-blif-gate-ff 
read_blif: Represent sequential elements with gate cells
 2025-09-29 08:21:16 -05:00
Jannis Harder 4bb4b6c662 verific: Extend -sva-continue-on-err to handle FSM explosion 
This also rolls back any added cells and wires, since we might have
added a lot of helper logic by the point we detect this.
 2025-09-27 21:13:02 +02:00
Jannis Harder 83dd99efb7 verific: New `-sva-continue-on-error` import option 
This option allows you to process a design that includes unsupported
SVA. Unsupported SVA gets imported as formal cells using 'x inputs and
with the `unsupported_sva` attribute set. This allows you to get a
complete list of defined properties or to check only a supported subset
of properties. To ensure no properties are unintentionally skipped for
actual verification, even in cases where `-sva-continue-on-error` is
used by default to read and inspect a design, `hierarchy -simcheck` and
`hierarchy -smtcheck` (run by SBY) now ensure that no `unsupported_sva`
property cells remain in the design.
 2025-09-24 18:58:54 +02:00
Robert O'Callahan 1e5f920dbd Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
Emil J a78eb9e151
Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort 
write_rtlil: don't sort
 2025-09-22 11:14:39 +02:00
Jannis Harder 79e05a195d verilog: Bufnorm cell backend and frontend support 
This makes the Verilog backend handle the $connect and $input_port
cells. This represents the undirected $connect cell using the `tran`
primitive, so we also extend the frontend to support this.
 2025-09-17 14:01:09 +02:00
Robert O'Callahan a1141f1a4c Remove some unnecessary .c_str() calls to the result of unescape_id() 2025-09-16 23:12:14 +00:00
Robert O'Callahan d276529d46 Remove .c_str() calls from parameters to log_file_info() 2025-09-16 23:06:28 +00:00
Robert O'Callahan 548deba259 Remove .c_str() calls from parameters to log_file_warning() 2025-09-16 23:03:45 +00:00
Robert O'Callahan a7c46f7b4a Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix() 2025-09-16 23:02:16 +00:00
Robert O'Callahan d1fd6de6da Remove .c_str() calls from parameters to log_header() 2025-09-16 23:00:42 +00:00
Robert O'Callahan 5ac6858f26 Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
Emil J. Tywoniak 73747f6928 read_verilog: add -relativeshare for synthesis reproducibility testing 2025-09-16 15:47:35 +02:00
Robert O'Callahan 1a367b907c Use fast path for 32-bit Const integer constructor in more places 2025-09-16 03:17:24 +00:00
Robert O'Callahan f65ca488ec Update frontends to avoid bits() 2025-09-16 03:17:23 +00:00
Xing Guo 3d2bb1db17 verilog_parser: replace manual AST node allocation with typed midrule actions 
Use Bison's typed midrule actions to construct AST_FCALL nodes
with std::unique_ptr, replacing manual 'new' and extra->ast_stack
management. This improves type safety, ensures proper ownership, and
eliminates potential memory leaks.

Ref: https://www.gnu.org/software/bison/manual/html_node/Typed-Midrule-Actions.html
 2025-09-13 11:23:42 +08:00
Jannis Harder 193b057983
Merge pull request #5341 from rocallahan/more-varargs-conversion 
More varargs conversion
 2025-09-12 18:09:42 +02:00
Jannis Harder dd9627ed05
Merge pull request #5336 from rocallahan/remove-log-cstr 
Remove `.c_str()` calls from `log()`/`log_error()`
 2025-09-12 14:09:48 +02:00
Robert O'Callahan f4699e2b10 Remove unnecessary c_str() calls from err_at_loc/warn_at_loc 2025-09-12 06:21:56 +00:00
Robert O'Callahan 8cd3c069d6 Use C++ stringf machinery in verilog_error 2025-09-12 06:21:56 +00:00
Robert O'Callahan 733b6f0124 Remove unnecessary usage of .c_str() in parameters to input_error() 2025-09-12 06:03:05 +00:00
Robert O'Callahan ad4ef8b775 Make AstNode::input_error use C++ stringf machinery 2025-09-12 06:01:32 +00:00
Robert O'Callahan e0ae7b7af4 Remove .c_str() calls from log()/log_error() 
There are some leftovers, but this is an easy regex-based approach that removes most of them.
 2025-09-11 20:59:37 +00:00
Xing Guo 9a6f25fb73 verilog_parser: Use unique_ptr<> to store the attribute list. 
We can get rid of the new / delete statements and free_attr() and we
don't need to manage the memory manually.
 2025-09-11 09:57:45 +08:00
Emil J 5278b9cfe1
Merge pull request #5332 from YosysHQ/parse_specify-rebased 
Add state_dependent_path_declaration so that `ifnone` can be parsed (rebased)
 2025-09-09 21:53:04 +02:00
Robert O'Callahan 9764fa5c41 Remove superfluous/wasteful .c_str()s in log_file_warning() filename parameter 2025-09-09 15:41:03 +02:00
Michael Kupfer 75316e8c49 Add state_dependent_path_declaration so that `ifnone` can be parsed 2025-09-09 13:04:52 +02:00
Jannis Harder c468ee7add
Merge pull request #5304 from rocallahan/idstring-stringf 
Support `IdString` parameters in `stringf()` and remove `.c_str()` in a lot of places
 2025-09-08 20:29:20 +02:00
Xing Guo c30fd46ea3 Fix handling of cases that look like sva labels again. 
Commit c8e0ac0 introduces a regression on handling case exprs that look
like sva labels.  After some debugging, we shouldn't push the identifier
ast node to the ast_stack, otherwise, we will get the following
assertion failure:

```
➜  /tmp yosys -p 'read -sv a1.v'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.57+1 (git sha1 baa61a146, clang++ 20.1.8 -fPIC -O3)

-- Running command `read -sv a1.v' --

1. Executing Verilog-2005 frontend: a1.v
Parsing SystemVerilog input from `a1.v' to AST representation.
ERROR: Assert `extra->ast_stack.size() == 1' failed in frontends/verilog/verilog_parser.y:709.
➜  /tmp cat a1.v
module test(input wire A);
  localparam TEST = 1;
  always_comb begin
    case (A)
      TEST: assert(1);
    endcase
  end
endmodule
```

We encountered this issue before but with a different error message[^1],

[^1]: https://github.com/YosysHQ/yosys/issues/862
 2025-09-05 11:54:13 +08:00
Robert O'Callahan c7df6954b9 Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00
Ethan Mahintorabi d10190606c verilog: Lower required bison version to 3.6 
We're currently on version 3.6 of bison at Google, and Yosys
still correctly builds with it. This should better reflect
the actual requirements rather than an overly restrictive
check. If features from 3.8 are required it seems like bumping
would be appropriate.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2025-08-21 08:26:33 +01:00
Ethan Mahintorabi 7f0130efce verilog: Fix missing sstream include 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2025-08-21 08:26:20 +01:00
Emil J dbb977aa8b
Merge pull request #5288 from YosysHQ/emil/demote-verilog-parser-errors-again 
verilog: demote some parser errors to warnings again
 2025-08-13 12:52:50 +02:00
Emil J. Tywoniak 1603828b30 verilog_parser: fix locations of warnings for restrict keyword 2025-08-13 10:56:48 +02:00
Emil J. Tywoniak 910ff3ff36 verilog: demote some parser errors to warnings again 2025-08-13 10:54:47 +02:00
Emil J. Tywoniak 8582136a45 simplify: fix $initstate segfault 2025-08-12 12:39:36 +02:00
Emil J. Tywoniak 642e041f77 const2ast: fix for consistency with previous diagnostics behavior 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 99ab73424d verilog_location: rename location to Location to avoid conflict with Pass::location 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 5195f81257 ast: fix import node 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak df8422d244 verilog_lexer: refactor 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 740ed3fc1c ast: refactor 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 646c45e6b8 ast: remove null_check as dead code 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 25d2a8ce3a simplify: simplify 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 97bc0088d8 simplify: std::gcd 2025-08-11 13:34:10 +02:00
Krystine Sherwin d3e33a3be5 simplify.cc: Drop unused debug prints 
At least the ones added by this PR.  There are some unused debug prints that are *changed* by this PR, but I've left them.
 2025-08-11 13:34:10 +02:00
Krystine Sherwin 9b882c32c1 frontends/ast: More usage of auto 
For consistency.
 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 5b62616b63 preproc: formatting 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 9a10f4c02f verilog_lexer, verilog_parser: remove comment 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak ae65b4fc84 verilog_lexer: fix fallthrough warning 2025-08-11 13:34:10 +02:00
Emil J 39c5c256c0 verilog_lexer: remove comment 
Co-authored-by: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com>
 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak abb8b8d28b preproc: formatting 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 85b5a7d08b verilog: fix build dependency graph 2025-08-11 13:34:10 +02:00
Gary Wong 4ffd05af6f verilog: add support for SystemVerilog string literals. 
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
 2025-08-11 13:34:10 +02:00
garytwong 105a3cd32d verilog: fix string literal regular expression (#5187) 
* verilog: fix string literal regular expression.

A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.

* verilog: add regression test for string literal regex bug.

Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af and fixed by 40aa7eaf).
 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 42b5c14e35 read_verilog, ast: use unified locations in errors and simplify dependencies 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak e6e680cd62 readme, verilog_parser: bison 3.8 and ubuntu 22.04 example 2025-08-11 13:34:10 +02:00
Krystine Sherwin 0f7080ebf8 dpicall.cc: Fix sans-plugin function call 2025-08-11 13:34:10 +02:00
Krystine Sherwin d2573f168d preproc.cc: Use full path for generated file 
Fixes out-of-tree builds.
 2025-08-11 13:34:10 +02:00
Krystine Sherwin 8e89eab9a2 preproc depends on parser 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 27899180a3 fixup! fixup! ast, read_verilog: unify location types, reduce filename copying 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 87352f97b2 fixup! ast, read_verilog: unify location types, reduce filename copying 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak ecec9a760b ast, read_verilog: unify location types, reduce filename copying 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 8bf750ecbb neater errors, lost in the sauce of source 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak b3bf588966 ast, read_verilog: refactoring 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 84f0c5da73 ast: fix new memory safety bugs from rebase 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 4a00169452 ast: ownership for string values 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak c8e0ac0c61 ast, read_verilog: ownership in AST, use C++ styles for parser and lexer 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak f27309136f Revert "verilog: fix string literal regular expression (#5187)" 
This reverts commit 834a7294b7.
 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 36491569d2 Revert "verilog: add support for SystemVerilog string literals." 
This reverts commit 5feb1a1752.
 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak 98b3316f55 Revert "verilog: fix parser "if" memory errors." 
This reverts commit 34a2abeddb.
 2025-08-11 13:34:09 +02:00
KrystalDelusion 7f0e864d44
Merge pull request #5265 from bhagwat-rahul/fix-package-import 
Support package import
 2025-08-08 09:32:54 +12:00
Rahul Bhagwat f12055d3e0
rm debug logs 2025-08-06 15:39:36 -04:00
Rahul Bhagwat 7e0157ba2b
fix whitespace issues 2025-08-06 15:32:36 -04:00
Rahul Bhagwat fe59b6d3db
add safety checks and better name matching 2025-08-04 20:57:43 -04:00
Jannis Harder 75b62d0164 verificsva: Fix typo in the cover only followed-by operator support 2025-08-04 15:38:19 +02:00
Rahul Bhagwat 761015b23e
add separate module test 2025-08-03 23:48:33 -04:00
Rahul Bhagwat b776283d79
implement package import 2025-08-03 23:31:54 -04:00
Miodrag Milanovic f92a53ec31 verific: handle nullptr for message_id 2025-07-30 10:51:54 +02:00
Mike Inouye 0314db80ea Correctly reset Verific flags to Yosys defaults after -import and warn this has occurred. 
Co-authored-by: Chris Pearce <chris@pearce.org.nz>
Signed-off-by: Mike Inouye <mikeinouye@google.com>
 2025-07-25 19:15:01 +00:00
KrystalDelusion 5b8b5292ee
Merge pull request #4959 from YosysHQ/krys/primitive_array_error 
simplify: Skip AST_PRIMITIVE in AST_CELLARRAY
 2025-07-21 10:26:00 +12:00
N. Engelhardt e47f5369fd verificsva: check -L value is small enough for code to work 2025-07-09 15:58:35 +02:00
KrystalDelusion 1a215719e5
Merge pull request #5192 from garytwong/multiline-string 
verilog: support newline and hex escapes in string literals
 2025-07-08 10:27:01 +12:00