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4784 Commits

Author SHA1 Message Date
Emil J. Tywoniak a24c260998 proc_mux, genrtlil: make use of case_src for better case condition vs block tracking 2026-01-26 12:50:51 +01:00
Emil J. Tywoniak 502ba3734b proc_mux: copy switch src to _CMP wire 2026-01-26 12:50:51 +01:00
Emil J. Tywoniak da65a18f39 proc_mux: copy mux src to Y port 2026-01-26 12:50:51 +01:00
Emil J. Tywoniak ee800087e8 proc_mux: add comments 2026-01-26 12:50:51 +01:00
Emil J. Tywoniak b3aea1b5d2 proc_mux: optimize source map locality for index density 2026-01-26 12:50:51 +01:00
Emil J. Tywoniak 4072bcfd0b proc_dff: add wire src attributes to dff cells 2026-01-26 12:50:51 +01:00
Emil J. Tywoniak 469083dcaa proc_mux: default to case src when action src is missing 2026-01-26 12:50:51 +01:00
Emil J. Tywoniak 778a667a91 proc_mux: refactor 2026-01-26 12:50:51 +01:00
Emil J. Tywoniak cacd584347 proc_mux: emit fused action location src attributes on procmuxes 2026-01-26 12:50:51 +01:00
Emil J. Tywoniak c36370f227 rtlil: add source tracking to CaseRule actions 2026-01-26 12:50:51 +01:00
Emil J. Tywoniak 94a53e08bc rtlil: replace SigSig actions with new type SyncAction 2026-01-26 12:50:51 +01:00
Emil J f5ea73eb97
Merge pull request #5557 from nataliakokoromyti/lut2mux-word 
lut2mux: add -word option
 2026-01-23 17:24:41 +01:00
KrystalDelusion 125609105d
Merge pull request #5593 from RCoeurjoly/RCoeurjoly/5574_fix 
abc: handle ABC script errors instead of hanging
 2026-01-23 07:16:48 +13:00
Emil J 317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon 
Add debugon pass for persistent debug logging
 2026-01-21 17:34:30 +01:00
Emil J 5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree 
Add opt_balance_tree pass
 2026-01-21 17:34:08 +01:00
Emil J. Tywoniak c3f36afe7f opt_balance_tree: mark experimental 2026-01-19 12:01:25 +01:00
Robert O'Callahan 28c199fbbd Fix warning about unused variable in `dffunmap`. 2026-01-19 03:25:09 +00:00
KrystalDelusion 8da8d681d0
Merge pull request #5544 from YosysHQ/krys/sim_check_eval_err 
Improve error handling in sim
 2026-01-19 09:51:12 +13:00
Natalia ed64df737b Add -on/-off modes to debug pass 2026-01-15 12:07:26 -08:00
Natalia 305b6c81d7 Refine width check to allow Y_WIDTH >= natural width 
Change from equality check to >= to allow cells where output
is wider than natural width (zero-extended). Only reject cells
with Y_WIDTH < natural width (truncated).

This fixes test failures while still preventing the truncation
issue identified in widlarizer's feedback.
 2026-01-14 14:58:53 -08:00
Natalia 60ac3670cb Fix truncation issue in opt_balance_tree pass 
Only allow rebalancing of cells with "natural" output widths (no truncation).
This prevents equivalence failures when moving operands between adders
with different intermediate truncation points.

For each operation type, the natural width is:
- Addition: max(A_WIDTH, B_WIDTH) + 1 (for carry bit)
- Multiplication: A_WIDTH + B_WIDTH
- Logic ops: max(A_WIDTH, B_WIDTH)

Fixes widlarizer's counterexample in YosysHQ/yosys#5605 where an 8-bit
intermediate wire was intentionally truncating adder results, and
rebalancing would change where that truncation occurred.
 2026-01-14 13:14:56 -08:00
Natalia Kokoromyti 6aef8ea8ab Add missing <deque> include for MSVC compatibility 2026-01-13 15:31:46 -08:00
nataliakokoromyti 8a596f330a Update lut2mux.cc 2026-01-13 15:02:17 -08:00
nataliakokoromyti 40f9e235de
Update lut2mux.cc 2026-01-13 14:45:46 -08:00
nataliakokoromyti 6a93a94d9f
fix line 2026-01-13 14:44:51 -08:00
nataliakokoromyti c305c426eb
restore extra_args 2026-01-13 14:43:52 -08:00
Natalia Kokoromyti 8b6925c5b0 Add opt_balance_tree pass for timing optimization 
This pass converts cascaded chains of arithmetic and logic cells ($add,
$mul, $and, $or, $xor) into balanced binary trees to improve timing
performance in hardware synthesis.

The optimization uses a breadth-first search approach to identify chains
of compatible cells, then recursively constructs balanced trees that
reduce the critical path depth.

Features:
- Supports arithmetic cells: $add, $mul
- Supports logic cells: $and, $or, $xor
- Command-line options: -arith (arithmetic only), -logic (logic only)
- Preserves signed/unsigned semantics
- Comprehensive test suite with 30 test cases

Original implementation by Akash Levy <akash@silimate.com> for Silimate.
Upstreamed from https://github.com/Silimate/yosys
 2026-01-13 14:20:11 -08:00
Emil J. Tywoniak 8e2038c419 Use digit separators for large decimal integers 2026-01-13 16:38:12 +01:00
Miodrag Milanović 51b210c93c
Merge pull request #5600 from YosysHQ/fix_musllinux 
musllinux fix so wheels build can work
 2026-01-13 07:08:04 +01:00
Emil J cc25ccfcd7
Merge pull request #5559 from nataliakokoromyti/upstream-lut2bmux 
add lut2bmux
 2026-01-12 16:09:13 +01:00
Miodrag Milanovic b3b71df07c musllinux fix so wheels build can work 2026-01-12 15:38:45 +01:00
Miodrag Milanović 72690062a1
Merge pull request #5599 from YosysHQ/musllinux_fix 
musllinux fix so wheels build can work
 2026-01-12 14:00:00 +01:00
Emil J f193dd0a28
Merge pull request #5594 from rocallahan/sdc-workaround 
Check for missing port in SDC code to work around compiler bug
 2026-01-12 11:22:25 +01:00
Miodrag Milanovic 2b12b74121 musllinux fix so wheels build can work 2026-01-11 15:23:38 +01:00
Robert O'Callahan 37347aacb2 Check for missing port in SDC code 
I am getting weird crashes on `main` in `tests/sdc/alu_sub.ys` which I traced to a null `Wire*`
in `SdcObjects::constrained_ports`. The null `Wire*` is being set in the `SdcObjects`
constructor. I don't understand what's going on here, so I added this check to detect the
missing wire early ... and that made the crash go away. Compiler bug maybe? I have
`Debian clang version 19.1.7 (3+build5)`, default build configuration.

Anyway this code seems fine to have.
 2026-01-10 04:00:17 +00:00
KrystalDelusion cc3d569ade
Merge pull request #5591 from YosysHQ/krys/clean_empty_switch 
Improve handling of empty switches
 2026-01-09 11:52:27 +13:00
Robert O'Callahan 8da919587d Parallelize `opt_merge`. 
I'm not sure why but this is actually faster than existing `opt_merge` even with
YOSYS_MAX_THREADS=1, for the jpeg synthesis test. 16.0s before, 15.5s after for
end-to-end synthesis.
 2026-01-08 04:21:39 +00:00
Roland Coeurjoly f1fc704c84 abc: handle ABC script errors instead of hanging 2026-01-07 23:46:33 +01:00
Krystine Sherwin c0e29ef57c
proc_clean: Removing an empty full_case is doing something 2026-01-07 13:10:32 +13:00
Emil J 0ab967b036
Merge pull request #5564 from rocallahan/pass-fuzz 
Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
 2026-01-06 20:07:31 +01:00
Emil J 5c630a366d
Merge pull request #5555 from rocallahan/defer-redirects 
Defer redirecting cell outputs when merging cells in `opt_merge` untill after we've done a full pass over the cells.
 2026-01-06 18:48:16 +01:00
Robert O'Callahan 042ec1cf60 Defer redirecting cell outputs when merging cells in `opt_merge` until after we've done a full pass over the cells. 
This avoids changing `assign_map` and `initvals`, which are inputs to the hash function for `known_cells`,
while `known_cells` exists. Changing the hash function for a hashtable while it exists leads to
confusing behavior. That also means the exact behavior of `opt_merge` cannot be reproduced by a
parallel implementation.
 2026-01-06 16:21:48 +00:00
Natalia 11b0e7ad92 add lut2bmux 2026-01-06 14:48:16 +01:00
Miodrag Milanović aa9991d3ee
Merge pull request #5571 from YosysHQ/micko/warning 
remove unused variable
 2025-12-23 16:32:10 +01:00
Miodrag Milanovic 4bc4e4eb41 remove unused variable 2025-12-23 15:47:35 +01:00
Natalia 721b504479 lut2mux: add -word option and test 2025-12-23 05:57:40 -08:00
Miodrag Milanović 09f9e0e8d1
Merge pull request #5568 from rocallahan/abc-spawn-errno 
Print `errno` to help diagnose failure to spawn ABC
 2025-12-23 08:09:14 +01:00
Robert O'Callahan 0e61f57458 Print errno to help diagnose failure to spawn ABC 2025-12-22 21:58:15 +00:00
N. Engelhardt d5b38af4a7
Merge pull request #5550 from YosysHQ/nak/dont_merge_properties 2025-12-22 16:54:43 +01:00
Robert O'Callahan 48cdb499f2 Remove `IdString::id_string()`. 
This was needed for the short time when `ID()` could return a value of `StaticIdString`.
That is no longer a problem.
 2025-12-22 01:57:30 +00:00