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16401 Commits

Author SHA1 Message Date
gatecat 45a6940f40 cxxrtl: Add debug items for state with private names 
Signed-off-by: gatecat <gatecat@ds0.me>
 2025-05-26 16:58:13 +02:00
George Rennie e0c1e88f19 kernel: use try_as_int to implement as_int_compress 2025-05-26 15:34:13 +01:00
George Rennie 353fd0f7f4 tests: test opt_expr for 32 bit unsigned shifts 2025-05-26 15:28:44 +01:00
George Rennie 33a22b5cd1 kernel: fix convertible_to_int for overflowing unsigned values 2025-05-26 15:28:14 +01:00
Emil J 4f7ea38b49
Merge pull request #5127 from RonxBulld/refine_strip 
Disable STRIP operations when appropriate.
 2025-05-26 15:03:34 +02:00
Krystine Sherwin 32ce23458f
read_verilog: Mark struct as custom type 
Being a custom type means that it will be resolved *before* (e.g.) a wire can use it as a type.
 2025-05-26 12:19:33 +12:00
Krystine Sherwin 995a893afd
Tests: Add svtypes/typedef_struct_global.ys 2025-05-26 12:16:58 +12:00
Gary Wong 73e45d29d6 Add semantic test cases for SystemVerilog priority/unique/unique0 "if". 
The tests/verilog/*_if_enc.ys scripts instantiate simple encoder
modules, both with and without the SystemVerilog priority/unique/unique0
keywords, and check for consistency between the two for the subset
of inputs where the priority/unique/unique0 "if" result is
well-defined.

These tests vacuously succeed at the moment, since priority/unique
keywords are silently ignored and therefore the generated logic is
trivially identical.  But the test cases will be capable of detecting
certain types of unsound optimisation if priority/unique handling is
introduced later.
 2025-05-24 08:44:04 -06:00
github-actions[bot] 209df95fb9 Bump version 2025-05-24 00:23:33 +00:00
Emil J 18abf2d4f7
Merge pull request #5138 from YosysHQ/emil/libcache-verbose 
libcache: add -quiet and -verbose
 2025-05-24 00:05:46 +02:00
Emil J 4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width 
rtlil: enable single-bit vector wires
 2025-05-23 15:55:45 +02:00
George Rennie e05b21cfae
Merge pull request #5140 from garytwong/typo-fix 
Fix typo ("exist" -> "exit").
 2025-05-23 13:01:57 +01:00
Gary Wong 9770ece187 Accept (and ignore) SystemVerilog unique/priority if. 
Add support to the "read_verilog -sv" parser to validate the
"unique", "unique0", and "priority" keywords in contexts where
they're legal according to 1800-2012 12.4.2.

This affects only the grammar accepted; the behaviour of conditionals
is not changed.  (But accepting this syntax will provide scope for
possible optimisations as future work.)

Three test cases ("unique_if", "unique_if_else", and
"unique_if_else_begin") verify that the keywords are accepted where
legal and rejected where illegal, as described in the final paragraph
of 12.4.2.
 2025-05-22 19:28:28 -06:00
Gary Wong 4f0cbf2ee6 Fix typo ("exist" -> "exit"). 2025-05-22 18:52:33 -06:00
github-actions[bot] 6c67b29bbb Bump version 2025-05-23 00:24:38 +00:00
George Rennie 6331f92d00
Merge pull request #5101 from georgerennie/george/opt_expr_shift_ovfl 
opt_expr: fix shift optimization with overflowing shift amount
 2025-05-22 15:16:19 +01:00
George Rennie 98eec36921 kernel: add comments to as_int family of methods 2025-05-22 15:12:13 +01:00
Emil J 4f33cc52db
Merge pull request #5137 from mikesinouye/assert 
Allow reading of gzipped files when not in NDEBUG
 2025-05-22 10:39:48 +02:00
Gus Smith d8b27d41c0 Bugfix 2025-05-21 21:31:07 -07:00
mikesinouye 761dc6f62a
Allow reading of gzipped files when not in NDEBUG 2025-05-21 15:18:29 -07:00
Krystine Sherwin 847558547b
functional.cc: Reverse port iteration 2025-05-21 16:21:27 +12:00
Krystine Sherwin 3001473ae5
functional.cc: Maintain port ordering 
Based on #4753.
 2025-05-21 16:09:39 +12:00
Gus Smith 8ec9de00ec Use ir.inputs()/ir.outputs() 2025-05-20 17:45:23 -07:00
Gus Smith af51097af7 Convert to 'assoc list helpers' 2025-05-18 18:01:43 -07:00
Gus Smith a55dc80175 Rename parameter 2025-05-17 16:04:17 -07:00
Gus Smith c1111f125c Add output helper as well 2025-05-17 15:19:09 -07:00
Gus Smith 1fdfba2a1a Add helper for accessing by base name 
The existing access function isn't useful if we don't have access to the original
names of the input/output/state signals. There may be a better way to do this, but
it might require restructuring the SmtrStruct.
 2025-05-17 15:17:29 -07:00
Gus Smith 10b8fdddb4 Rename argument 2025-05-17 14:39:11 -07:00
Gus Smith 7b4c9c5dcd Add optional keyword-based constructor 2025-05-17 14:12:09 -07:00
Gus Smith fd5918c811 get_field_names for structs 2025-05-17 14:10:23 -07:00
RonxBulld 64a115e6f0
Disable STRIP operations when appropriate. 2025-05-18 01:07:06 +08:00
github-actions[bot] 388955031f Bump version 2025-05-17 00:23:43 +00:00
KrystalDelusion 135320a58c
Merge pull request #5123 from cr1901/winstat-fix 
Strip trailing slashes when checking for directories on Windows.
 2025-05-17 09:33:18 +12:00
William D. Jones 7d4d544001 Strip trailing slashes when checking for directories on Windows. 2025-05-15 18:36:43 -04:00
KrystalDelusion 4c72b0ecd8
Merge pull request #5116 from YosysHQ/krys/update_fst 
Update fstlib
 2025-05-16 09:22:52 +12:00
KrystalDelusion 3a5ce2df64
Merge pull request #5112 from YosysHQ/krys/on_shutdown 
design.cc: Use on_shutdown method
 2025-05-16 09:22:39 +12:00
KrystalDelusion f7888c607b
Merge pull request #5089 from YosysHQ/krys/cutpoint_whole 
cutpoint: Re-add whole module optimization
 2025-05-16 09:22:28 +12:00
Emil J 3823157c25
Merge pull request #5080 from akashlevy/muldiv_c 
Add `muldiv_c` peepopt
 2025-05-15 11:03:25 +02:00
github-actions[bot] ae47c49af5 Bump version 2025-05-15 00:22:59 +00:00
George Rennie 748600c167
small whitespace cleanup (#5119) 2025-05-14 15:18:57 +02:00
github-actions[bot] e3ae7b1400 Bump version 2025-05-13 00:24:04 +00:00
KrystalDelusion 5268565410
Merge pull request #5108 from marzoul/adrien-uram 
Create a single-port URAM mapping to support memories 2048 x 144b
 2025-05-13 09:54:36 +12:00
KrystalDelusion c590c0c12c
Merge pull request #5111 from YosysHQ/krys/config_python 
Makefile: Conditional assignment of python exe
 2025-05-13 09:54:26 +12:00
KrystalDelusion 05157b164e
Merge pull request #5113 from YosysHQ/krys/ast_asan 
simplify.cc: Fix mem leak
 2025-05-13 09:52:51 +12:00
Emil J. Tywoniak f73c6a9c9a write_verilog: don't dump single_bit_vector attribute 2025-05-12 13:36:25 +02:00
Emil J. Tywoniak e5171d6aa1 verific: support single_bit_vector 2025-05-12 13:23:29 +02:00
Emil J. Tywoniak 5e72464a15 rtlil: enable single-bit vector wires 2025-05-12 13:23:29 +02:00
Krystine Sherwin afd5bbc7fa
fstdata.cc: Fix last step 
Includes test file for sanity checking simulation steps.
 2025-05-12 13:18:19 +12:00
Krystine Sherwin d0b9a0cb98
sim.cc: Move cycle check 
Calling `throw dst_end_of_data_exception()` when the desired number of cycles has been reached means that the fst reader can't tidy up after itself and leads to memory leaks.
This doesn't happen when the `-stop` flag is used because the `Yosys::FstData` struct tracks the end time and skips the outer callback if the simulation has gone past the desired end time.
Move cycle checking into the inner callback along with the time checking means that the outer callback no longer needs to throw an exception in order to stop checking further values, while still allowing the fst reader to finish reading and deallocate memory.
 2025-05-12 12:48:01 +12:00
Krystine Sherwin cc402ee065
libs/fst: Update upstream 
libfst is no longer included in gtkwave and instead has its own repo.  There has also been some refactoring, so the patches need to update to match, as does sim.cc.
 2025-05-12 10:21:06 +12:00