yosys

Author	SHA1	Message	Date
Richard Herveille	2893938355	Removed SystemVerilog module end label	2024-03-19 01:31:36 +01:00
Richard Herveille	2d11c5e2f8	removed comment	2024-03-15 01:48:06 +01:00
Richard Herveille	58b1522a20	Added DSP macros	2024-03-06 02:45:29 +01:00
Claire Xenia Wolf	72787f52fc	Fixing old e-mail addresses and deadnames s/((Claire\|Xen\|Xenia\|Clifford)\s+)+(Wolf\|Xen)\s+<(claire\|clifford)@(symbioticeda.com\|clifford.at\|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina\|Nak\|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com\|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave\|david)@(symbioticeda.com\|yosyshq.com\|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag\|micko)@(symbioticeda.com\|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;	2021-06-08 00:39:36 +02:00
Larry Doolittle	50bcd9a728	Clean whitespace and permissions in techlibs/intel	2017-10-05 16:23:49 +02:00
dh73	cbaba62401	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now	2017-10-01 11:04:17 -05:00