The lexer for liberty files was using istream's `get` and `unget` which
are notorious for bad performance and that showed up during profiling.
This replaces the direct `istream` use with a custom LibertyInputStream
that does its own buffering to provide `get` and `unget` that behave the
same way but are implemented with a fast path that is easy to inline and
optimize.
Instead, change the default `Design::selected_modules()` to match the behaviour (i.e. `selected_unboxed_modules_warn()`) because it's a lot of files to touch and they don't really _need_ to be updated.
Also change `Design::selected_whole_modules()` users over to `Design::selected_unboxed_whole_modules()`, except `attrmap` because I'm not convinced it should be ignoring boxes. So instead, leave the deprecation warning for that one use and come back to the pass another time.
Used to select all modules including boxes, set when both `full` and `boxes` are true in the constructor, pulling down `full_selection`.
Add `Selection::selects_all()` method as short hand for `full_selection || complete_selection`.
Update selection operations to account for complete selections.
Add static methods to `Selection` for creating a new empty/full/complete selection to make it clearer to users when doing so.
Use said static methods to replace most instances of the `Selection` constructor.
Update `Selection::optimize` to use
New methods on Design to push/pop selection instead of accessing the selection stack directly. Includes methods for pushing a full/complete/empty selection.
Also helper methods on modules to check `is_selected` and `is_selected_whole`.
Now uses two enums, one to control whether or not to include partially selected
modules (and what to do if they are encountered), and one to control whether or
not to include boxed modules (and what to do if they are encountered).
Mark Design::selected{modules, whole_modules}() deprecated and make them
provide warnings on boxes. There are a lot of places that use them and I can't
always tell which ones support boxed modules and which don't.
The `Design::selected_*()` methods no longer unconditionally skip boxed modules. Instead, selections are now box and design aware.
The selection constructor now optionally takes a design pointer, and has a new `selects_boxes` flag. If the selection has an assigned design, then `Selection::selected_*()` will only return true for boxed modules if the selects_boxes flag is set. A warning is raised if a selection is checked and no design is set. Selections can change design via the `Selection::optimize()` method.
Most places that iterate over `Design::modules()` and check `Selection::selected_module()` should instead use `Design::selected_modules()`.
Since boxed modules should only ever be selected explicitly, and `full_selection` (now) refers to all non-boxed modules, `Selection::optimize()` will clear the `full_selection` flag if the `selects_boxes` flag is enabled, and instead explicitly selects all modules (including boxed modules). This also means that `full_selection` will only get automatically applied to a design without any boxed modules.
These changes necessitated a number of changes to `select.cc` in order to support this functionality when operating on selections, in particular when combining selections (e.g. by union or difference).
To minimize redundancy, a number of places that previously iterated over `design->modules()` now push the current selection to the design, use `design->selected_modules()`, and then pop the selection when done.
Introduce `RTLIL::NamedObject`, to allow for iterating over all members of a module with a single iterator instead of needing to iterate over wires, cells, memories, and processes separately.
Also implement `Module::selected_{memories, processes, members}()` to match wires and cells methods. The `selected_members()` method combines each of the other `selected_*()` methods into a single list.
`b_width_capped` already exists for preventing arithmetic overflow, limiting the value of `b_width` to 30. This just changes the left shifts to also use it.
The caveat of incorrect results for extremely large values of `a_width` still applies, as does the improbability of that actually happening.
This fixes#4844 (or at least, the floating point exception; the circuit still isn't valid but I think that's fine).
In the current documentation, it's unclear if `result.string` serves as
an example of a string name. It is furthermore unclear what the purpose
of `result.string` is. Clarify this by adding a small explanation (and
fix a typo)
The B port is for single-bit summands. These can just as well be
represented as an additional summand on the A port (which supports
summands of arbitrary width). An upcoming `$macc_v2` cell won't be
special-casing single-bit summands in any way.
In preparation, make the following changes:
* remove the `bit_ports` field from the `Macc` helper (instead add any
single-bit summands to `ports` next to other summands)
* leave `B` empty on cells emitted from `Macc::to_cell`
In commit ac988cf we made sure to undefine the CONST/VOID macros left
defined by `tcl.h`, but this in turn makes it an issue to include
additional Tcl headers later on (see issue #4808).
One way out is to avoid a global `tcl.h` include. In the process we drop
support for Tcl-enabled MXE builds, which were likely broken anyway due
to the additional Tcl APIs used from `tclapi.cc`.
Drop the parts that are being dropped.
Move the things that are being moved.
Also move the verilog stuff out of README and into the docs.
GettingStarted is less cut and dry, so hold off on that one.
Avoid error:
```
kernel/mem.cc:1683:7: error: conflicting declaration ‘using addr_t = using addr_t = uint32_t’
1683 | using addr_t = MemContents::addr_t;
| ^~~~~~
In file included from /usr/include/sys/types.h:222,
from /usr/include/pthread.h:11,
from /usr/lib/gcc/x86_64-pc-cygwin/12/include/c++/x86_64-pc-cygwin/bits/gthr-default.h:35,
from /usr/lib/gcc/x86_64-pc-cygwin/12/include/c++/x86_64-pc-cygwin/bits/gthr.h:148,
from /usr/lib/gcc/x86_64-pc-cygwin/12/include/c++/ext/atomicity.h:35,
from /usr/lib/gcc/x86_64-pc-cygwin/12/include/c++/bits/cow_string.h:37,
from /usr/lib/gcc/x86_64-pc-cygwin/12/include/c++/bits/basic_string.h:51,
from /usr/lib/gcc/x86_64-pc-cygwin/12/include/c++/string:53,
from ./kernel/yosys_common.h:27,
from ./kernel/yosys.h:42,
from ./kernel/mem.h:23,
from kernel/mem.cc:20:
/usr/include/machine/types.h:63:15: note: previous declaration as ‘typedef char* addr_t’
63 | typedef char *addr_t;
```
According to IntelliSense, only the return types need to be prefixed with `MemContents::`, the rest are automagically using the class definition and highlight as `using Yosys::MemContents::addr_t = uint32_t`.
`Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`.
For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
There's a mismatch between what `kernel/mem.cc` emits for memories
with no read ports and what the internal RTLIL check expects.
The point of dispute it whether some of the parameters relating to read
ports have a zero-width value in this case. The `mem.cc` code says no,
the internal checker says yes.
Surveying the other `$mem_v2` parameters, and internal cell parameters
in general, I am inclined to side with the `mem.cc` code.
This breaks RTLIL compatibility but for an obscure edge case.
Initialize "unsigned int inner" in hash() functions
Includes a log_assert() that might help catch corrupted data structures
or future incomplete modification of DriveType definition
Remove `/source/cell` from .gitignore.
Add a few initial cell pages.
Add YosysCellGroup documenter and cell:group directive.
Update Documenters to use nested json.
Better nested tocs for group.module.source layout.
New `help -dump-cells-json <file>` to dump cells list.
Add 'group' field to SimHelper class/struct with defaults to gate_other and word_other depending on source (simcells or simlib).
Add 'unary' group to unary operator cells for testing (based on internal cell library docs page).
- Drop `cell_code` and instead map code lookups to the `cell_help` dict.
- Add helper functions to struct for checking and getting the right cell.
- Add `CellType` for cell to `write_cell_rst` function declaration in
preparation for use in future.
- Iterate over `yosys_celltypes.cell_types` when exporting cell rst files,
reporting errors for any cells defined in `cell_types` but not
`cell_help_messages`.
Since `simcells.v` uses consistent formatting we can handle it specifically to help tidy up sphinx warnings about the truth tables, and instead chuck them in a code block which when printing to rst.
Also has the side effect that rst code blocks can be added manually with `//- ::` followed by a blank line.
Include Source file and line number in SimHelper struct, and use it for verilog code caption in rst dump.
Also reformat python string conversion to iterate over a list of fields instead of repeating code for each.
Allows for more expressive code when constructing help messages for cells.
Will also move extra logic in parsing help strings into the initial python parse instead of doing it in the C++ at export time.
Krystine Sherwin
Miodrag Milanović
Jannis Harder
Emil J. Tywoniak
Martin Povišer
N. Engelhardt
David Sawatzke
mikesinouye
Robin Ole Heinemann
Larry Doolittle
Lofty
Philippe Sauter