luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 11:18:31 +02:00
Code Issues Packages Projects Releases Wiki Activity
13,741 Commits 154 Branches 70 Tags
3b63ab07ae289397573d32f2851cd78aedeeea94
Commit Graph
1 Commits
Author SHA1 Message Date
Udi Finkelstein 536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
 2018-10-25 02:37:56 +03:00