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328 Commits

Author SHA1 Message Date
Eddie Hung 5466121ffb Capture all data in one "abc_flop" attribute 2019-07-01 11:50:14 -07:00
Eddie Hung 659c04a68d Update abc_box_id numbering 2019-07-01 10:47:14 -07:00
Eddie Hung 699d8e3939 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-07-01 10:44:42 -07:00
Eddie Hung dd8d264bf5 install *_nowide.lut files 2019-06-29 19:37:04 -07:00
Eddie Hung 728839d6ca Remove peepopt call in synth_xilinx since already in synth -run coarse 2019-06-28 12:53:38 -07:00
Eddie Hung 00f63d82ce Reduce diff with upstream 2019-06-27 16:13:22 -07:00
Eddie Hung 9398921af1 Refactor for one "abc_carry" attribute on module 2019-06-27 16:07:14 -07:00
Eddie Hung 312c03e4ca Remove redundant doc 2019-06-27 15:28:55 -07:00
Eddie Hung 1237a4c116 Add warning if synth_xilinx -abc9 with family != xc7 2019-06-27 11:22:49 -07:00
Eddie Hung 6c256b8cda Merge origin/master 2019-06-27 11:20:15 -07:00
Eddie Hung a7a88109f5 Update comment on boxes 2019-06-26 20:00:15 -07:00
Eddie Hung b7bef15b16 Add "WE" to dist RAM's abc_scc_break 2019-06-26 19:58:09 -07:00
Eddie Hung 5e1b8d458b Remove unused var 2019-06-26 10:33:07 -07:00
Eddie Hung 988e6163ab Add _nowide variants of LUT libraries in -nowidelut flows 2019-06-26 10:23:29 -07:00
Eddie Hung 799b18263f Merge branch 'koriakin/xc7nocarrymux' into xaig 2019-06-26 10:04:01 -07:00
Eddie Hung 7389b043c0 Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriakin/xc7nocarrymux 2019-06-26 09:33:38 -07:00
Eddie Hung 480a04cb3c Realistic delays for RAM32X1D too 2019-06-25 09:34:28 -07:00
Eddie Hung 6095357390 Add RAM32X1D box info 2019-06-25 09:34:19 -07:00
Eddie Hung 6f36ec8ecf Merge remote-tracking branch 'origin/master' into xaig 2019-06-25 09:33:11 -07:00
Eddie Hung 2f770b7400 Use LUT delays for dist RAM delays 2019-06-24 23:02:53 -07:00
Eddie Hung 152e682bd5 Add Xilinx dist RAM as comb boxes 2019-06-24 21:54:01 -07:00
Eddie Hung efd04880db Add RAM32X1D support 2019-06-24 16:16:50 -07:00
Eddie Hung 792d0670c3 Add comment to xc7 box 2019-06-22 14:28:24 -07:00
Eddie Hung 7903ebe3e0 Carry in/out box ordering now move to end, not swap with end 2019-06-22 14:18:42 -07:00
Eddie Hung 65c022c257 Remove DFF and RAMD box info for now 2019-06-21 20:41:14 -07:00
Eddie Hung f11c9a419b Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc 2019-06-20 17:38:16 -07:00
Eddie Hung 8e0a47fb92 Really permute Xilinx LUT mappings as default LUT6.I5:A6 2019-06-18 11:48:48 -07:00
Eddie Hung 8f5e6d73ff Revert "Fix (do not) permute LUT inputs, but permute mux selects" 
This reverts commit da3d2eedd2.
 2019-06-18 11:35:21 -07:00
Eddie Hung da3d2eedd2 Fix (do not) permute LUT inputs, but permute mux selects 2019-06-18 09:49:57 -07:00
Eddie Hung 608a95eb01 Fix copy-pasta issue 2019-06-17 22:29:22 -07:00
Eddie Hung 2a35c4ef94 Permute INIT for +/xilinx/lut_map.v 2019-06-17 22:24:35 -07:00
Eddie Hung 75f8b4cf10 Simplify comment 2019-06-17 19:14:41 -07:00
Eddie Hung 75d92fb590 Merge branch 'xaig' into xaig_dff 2019-06-17 19:11:07 -07:00
Eddie Hung 840562943f Update LUT7/8 delays to take account for [ABC]OUTMUX delay 2019-06-17 17:06:01 -07:00
Eddie Hung 8a86f9bb62 Add box delays for FD* 2019-06-17 15:13:05 -07:00
Eddie Hung 5ce672d1c5 Merge remote-tracking branch 'origin/xaig' into xaig_dff 2019-06-17 12:14:55 -07:00
Eddie Hung c15ee827f4 Try -W 300 2019-06-17 10:29:06 -07:00
Eddie Hung 0c59bc0b75 Cleanup 2019-06-16 10:42:00 -07:00
Eddie Hung d969a9060e Add +/xilinx/abc_ff 2019-06-15 22:41:29 -07:00
Eddie Hung 9ec57b46c2 Fix spacing 2019-06-15 19:36:37 -07:00
Eddie Hung c2f3f116d0 Use $__ABC_FF_ instead of $_FF_ 2019-06-15 18:16:14 -07:00
Eddie Hung 65c7bafc64 Re-order alphabetically 2019-06-15 10:19:05 -07:00
Eddie Hung a76c8a7ffd Fix initialisation of flops 2019-06-15 09:46:35 -07:00
Eddie Hung ac18a76beb Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues 2019-06-15 09:34:48 -07:00
Eddie Hung 295bb23ae0 Wrap FDRE with $__ABC_FDRE containing comb 2019-06-15 09:08:56 -07:00
Eddie Hung bf312043d4 Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O 2019-06-15 05:45:16 -07:00
Eddie Hung 8fa74287a7 As per @daveshah1 remove async DFF timing from xilinx 2019-06-14 12:43:20 -07:00
Eddie Hung 2e34859a6b Add XC7_WIRE_DELAY macro to synth_xilinx.cc 2019-06-14 11:38:22 -07:00
Eddie Hung ba4b4a0088 Update delays based on SymbiFlow/prjxray-db 2019-06-14 11:33:10 -07:00
Eddie Hung d47ff7ba87 Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut} 2019-06-14 10:51:11 -07:00