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4143 Commits

Author SHA1 Message Date
Akash Levy 35c19cb391 Option to include unused bits attribute or not 2024-08-14 22:05:12 -07:00
Akash Levy 34e5bc1129
Merge branch 'YosysHQ:main' into master 2024-08-14 16:56:53 -07:00
Akash Levy 71a7f3fabd Fix for segfaulting 2024-08-14 16:00:03 -07:00
Akash Levy 8118380726 Update to fix infinite loop 2024-08-14 13:40:30 -07:00
Akash Levy 83dfdd9dd5 Fix splitfanout 2024-08-14 13:19:58 -07:00
Akash Levy 63a421aed8 Small comment update 2024-08-14 05:37:28 -07:00
Akash Levy 2deabdd640 Make splitfanout more robust 2024-08-14 05:29:03 -07:00
Akash Levy 55782682de Iterative muxpack 2024-08-14 05:27:50 -07:00
Akash Levy 5777bed8ed Add splitfanout first pass 2024-08-14 03:24:24 -07:00
Martin Povišer 3057c13a66 Improve libparse encapsulation 2024-08-13 18:47:36 +02:00
Martin Povišer 78382eaa6f libparse: Adjust whitespace 2024-08-13 18:47:36 +02:00
Akash Levy 953f405a84
Merge branch 'YosysHQ:main' into master 2024-08-07 11:47:52 -07:00
Martin Povišer 4c3203866f exec: Add missing newline 2024-08-07 13:02:00 +02:00
Akash Levy 36fb6e08c1 Make muxpack faster 2024-08-06 02:26:57 -07:00
Akash Levy b4ae5e8574
Merge branch 'YosysHQ:main' into master 2024-08-05 11:02:17 -07:00
Miodrag Milanovic 6d98418f3d Set ranges on exported wires in VCD and FST 2024-08-02 15:23:00 +02:00
Akash Levy bafce0ddee Revert SCC 2024-07-30 23:08:06 -07:00
Akash Levy c0af4604bc Update Yosys 2024-07-30 16:55:18 -07:00
Emil J 92cac63845
Merge pull request #4344 from widlarizer/emil/keep_hierarchy 
cost: add keep_hierarchy pass with min_cost argument
 2024-07-29 16:33:08 +02:00
N. Engelhardt 9f869b265c
Merge pull request #4474 from tony-min-1/mchp 
Add PolarFire FPGA support
 2024-07-29 15:28:44 +02:00
Emil J. Tywoniak 4b29f64142 cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter 2024-07-29 10:26:02 +02:00
Akash Levy 89630d3755
Merge branch 'YosysHQ:main' into master 2024-07-28 22:42:33 -07:00
N. Engelhardt dd3637f9f0
Merge pull request #4506 from povik/synthprop-formatting 
synthprop: Reformat the help
 2024-07-26 12:28:09 +02:00
Martin Povišer 7ee685a0b0 proc_rom: Set `src` on the emitted memory 2024-07-25 23:14:27 +01:00
Akash Levy 0a997b9e64 muxpack verbosity and -ignore_excl option 2024-07-25 04:40:37 -07:00
Martin Povišer e063b96104 synthprop: Reformat the help 2024-07-25 11:43:58 +02:00
Akash Levy a42f4dbedb
Merge branch 'YosysHQ:main' into master 2024-07-18 00:10:20 -07:00
Emil J 1166238c0f
Merge pull request #4176 from povik/opt_expr-performance 
Improve `opt_expr` performance
 2024-07-15 16:10:25 +02:00
Emil J. Tywoniak 532188f239 opt_expr: change info message 2024-07-15 11:14:47 +02:00
Tony Min d41688f7d7
Revisions (#4) 
* area should be 1 for all LUTs

* clean up macros

* add log_assert to fail noisily when encountering oddly configured DFF

* clean help msg

* flatten set to true by default

* update

* merge mult tests

* remove redundant test

* move all dsp tests to single file and remove redundant tests

* update ram tests

* add more dff tests

* fix c++20 compile errors

* add option to dump verilog

* default to use abc9

* remove -abc9 option since its the default now

---------

Co-authored-by: tony <minchunlin@gmail.com>
 2024-07-08 10:57:16 -04:00
Akash Levy aec3df36d1 Make flatten less expressive 2024-07-07 21:46:23 -07:00
Akash Levy c85b8a8a4d
Merge branch 'YosysHQ:main' into master 2024-07-06 15:12:11 -07:00
N. Engelhardt dac5bd1983
Merge pull request #4455 from phsauter/shiftadd-limit-padding 
peepopt: limit padding from shiftadd
 2024-07-06 08:10:25 +02:00
C77874 d0cd01adfe fixed typos, build with makefile succeeds 2024-07-04 09:33:58 -07:00
C77874 0bb7d1373f changes made to filenames + references 2024-07-04 08:53:41 -07:00
Chun Lin Min e5bdc9b5c9 remove DSP48 references 2024-07-03 07:20:29 -07:00
Chun Lin Min 2ced2752e9 replace space indent with tab indent 2024-07-02 13:47:18 -07:00
Chun Lin Min acddc36389 add PolarFire FPGA support 2024-07-02 12:44:30 -07:00
Akash Levy 0596766cbd Merge upstream yosys changes 2024-07-01 18:33:38 -07:00
Catherine 580aaa362d
opt_lut_ins: fix name of global object. NFCI 2024-06-28 15:12:36 +00:00
Emil J. Tywoniak 01f332e750 opt_expr: reduce mostly harmless warning to log 2024-06-25 20:18:49 +02:00
Martin Povišer fa4a2b6b0d opt_expr: In clkinv loop ignore irrelevant cells early 
Each call to `handle_clkpol_celltype_swap` has a conversion of the
cell's type ID to an allocated string. This can sum up to a
non-negligible time being spent in the clkpol code even for a design
which doesn't have any flip-flop gates.
 2024-06-24 18:32:33 +02:00
Martin Povišer 7a8a69b65c opt_expr: Revisit sorting in `replace_const_cells` 
Avoid building a cell-to-inbit map when sorting the cells, add a warning
if we are unable to sort, and move the code treating non-combinational
cells ahead of the rest (this means we don't need to pass
non-combinational cells to the TopoSort object at all).
 2024-06-24 18:32:33 +02:00
Akash Levy 6795c32167 Make scopeinfo not default 2024-06-19 04:05:02 -07:00
Akash Levy 983d404e93 Smallfix 2024-06-17 20:04:38 -07:00
Akash Levy c8dff00ca6 Smallfix 2024-06-17 16:07:26 -07:00
Akash Levy 719bbd7523 Improve SCC reporting 2024-06-17 14:18:41 -07:00
Akash Levy e23e33441f Update yosys from upstream 2024-06-15 14:23:24 -07:00
Akash Levy fce46d2a53 Add better Yosys/Verific name aliasing and reenable dffe opt 2024-06-15 14:18:33 -07:00
Philippe Sauter 2f0f10cb87 peepopt: limit padding from shiftadd 
The input to a shift operation is padded.
This reduced the final number of MUX cells
but during techmap it can create huge
temporary multiplexers in the log shifter.
This significantly increases runtime and resources.

A limit is added with a warning when it is used.
 2024-06-14 15:33:03 +02:00