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18230 Commits

Author SHA1 Message Date
Akash Levy 0b47da5969 Smallfix 2024-07-01 12:51:46 -07:00
George Rennie 78ae4ed9ac hashlib: Add some more primes 
* Add some primes as suggested in #4458. This allows larger hashtables
  to be allocated for very big designs
 2024-07-01 12:37:41 +01:00
Akash Levy 5def05a5dd Smallfix 2024-07-01 04:20:52 -07:00
Akash Levy fe0c3b0ae1 Update verific 2024-07-01 03:38:59 -07:00
Akash Levy fee4caafb7 Don't display on stdout in py_wrap_generator when using log_to_stream 2024-07-01 02:29:49 -07:00
github-actions[bot] a739e21a5f Bump version 2024-06-29 00:16:56 +00:00
Catherine 580aaa362d
opt_lut_ins: fix name of global object. NFCI 2024-06-28 15:12:36 +00:00
Akash Levy dec43679be See if this fixes issues on Innatera design 2024-06-28 03:13:38 -07:00
Martin Povišer 07daf61ae6
Merge pull request #4467 from povik/fix-add-shiftx 
rtlil: Fix `addShiftx` for signed shifts
 2024-06-26 18:17:28 +02:00
Emil J. Tywoniak 01f332e750 opt_expr: reduce mostly harmless warning to log 2024-06-25 20:18:49 +02:00
github-actions[bot] 1288166f7a Bump version 2024-06-25 00:17:11 +00:00
Miodrag Milanović 1e401c3e04
Merge pull request #4460 from YosysHQ/micko/c++17 
Make C++17 compiler required
 2024-06-24 19:54:30 +02:00
Martin Povišer fa4a2b6b0d opt_expr: In clkinv loop ignore irrelevant cells early 
Each call to `handle_clkpol_celltype_swap` has a conversion of the
cell's type ID to an allocated string. This can sum up to a
non-negligible time being spent in the clkpol code even for a design
which doesn't have any flip-flop gates.
 2024-06-24 18:32:33 +02:00
Martin Povišer 7a8a69b65c opt_expr: Revisit sorting in `replace_const_cells` 
Avoid building a cell-to-inbit map when sorting the cells, add a warning
if we are unable to sort, and move the code treating non-combinational
cells ahead of the rest (this means we don't need to pass
non-combinational cells to the TopoSort object at all).
 2024-06-24 18:32:33 +02:00
Miodrag Milanovic 777624ccf5 Make yosys-config dependant of Makefile 2024-06-24 16:08:08 +02:00
Martin Povišer 89d939334e rtlil: Fix `addShiftx` for signed shifts 
Only the `B` input (the shift amount) can be marked as signed on a
`$shiftx` cell. Adapt the helper accordingly and prevent it from
creating invalid RTLIL when called with `is_signed` set. Previously
it would mark both `A` and `B` as signed.
 2024-06-21 15:14:08 +02:00
github-actions[bot] 6c8ae44ae7 Bump version 2024-06-20 00:17:08 +00:00
gatecat 22d8df1e7e liberty: Support for IO liberty files for verification 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-06-19 21:12:42 +02:00
Akash Levy 6795c32167 Make scopeinfo not default 2024-06-19 04:05:02 -07:00
Akash Levy e093ac5bca Update verific 2024-06-19 00:56:27 -07:00
github-actions[bot] ede3750a6c Bump version 2024-06-19 00:17:13 +00:00
Miodrag Milanović 8024688b1d
Merge pull request #4459 from YosysHQ/micko/vanilla_verific 
Verific build support improvements
 2024-06-18 10:50:20 +02:00
Akash Levy 983d404e93 Smallfix 2024-06-17 20:04:38 -07:00
Akash Levy c8dff00ca6 Smallfix 2024-06-17 16:07:26 -07:00
Akash Levy 719bbd7523 Improve SCC reporting 2024-06-17 14:18:41 -07:00
Miodrag Milanovic 2bbf3112d9 Update VS build to C++17 build 2024-06-17 17:29:20 +02:00
Martin Povišer f9b7b8fff0 Update documentation for C++17 switch 2024-06-17 17:08:13 +02:00
Miodrag Milanovic 141a2e3638 Make C++17 compiler required 2024-06-17 16:55:36 +02:00
Miodrag Milanovic dfde792288 Refactored import code 2024-06-17 14:49:58 +02:00
Miodrag Milanovic 19da7f7d59 Update makefile to make options uniform 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 0f3f731254 Handle -work for vhdl, and clean messages 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 0a81c8e161 Import all modules from all libraries when when needed 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 7c3094633d Compile with hier_tree separate SV and VHDL as well 2024-06-17 13:29:11 +02:00
Miodrag Milanovic e2e189647f Cleanup 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 7bec332b68 SV + VHDL with RTL support 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 25d50bb2af VHDL only build support 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 54bf9ccf06 Add initial support for Verific without additional YosysHQ patch 2024-06-17 13:29:11 +02:00
Akash Levy a0c0384683 Preserve instances 2024-06-16 20:20:10 -07:00
Akash Levy e23e33441f Update yosys from upstream 2024-06-15 14:23:24 -07:00
Akash Levy fce46d2a53 Add better Yosys/Verific name aliasing and reenable dffe opt 2024-06-15 14:18:33 -07:00
Philippe Sauter 2f0f10cb87 peepopt: limit padding from shiftadd 
The input to a shift operation is padded.
This reduced the final number of MUX cells
but during techmap it can create huge
temporary multiplexers in the log shifter.
This significantly increases runtime and resources.

A limit is added with a warning when it is used.
 2024-06-14 15:33:03 +02:00
Philippe Sauter 74e504330a peepopt: fix sign check in shiftadd 2024-06-14 13:01:18 +02:00
N. Engelhardt 74a1dd99ac
Merge pull request #4444 from YosysHQ/krys/scripting_docs 
Document script parsing
 2024-06-14 09:53:24 +02:00
github-actions[bot] 2fd2b6538d Bump version 2024-06-14 00:17:13 +00:00
Akash Levy 2337d97977 Sub1 fix 2024-06-13 15:33:17 -07:00
phsauter 34b5c6d062 peepopt: avoid shift-amount underflow 2024-06-13 23:30:07 +02:00
Asherah Connor 62bff3a204 cxxrtl: don't need to specify a value for "path". 
Callers of the deprecated method had a path already.
 2024-06-13 13:17:02 +01:00
Asherah Connor 3ed2865ac5 cxxrtl: capi: don't use deprecated invocation. 2024-06-13 13:17:02 +01:00
George Rennie 41aaaa153e peepopt shiftadd: Only match for sufficiently small constant widths 
This addresses issue #4445
 2024-06-12 14:38:12 +01:00
github-actions[bot] a55e8594b7 Bump version 2024-06-12 00:17:25 +00:00