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64 Commits

Author SHA1 Message Date
Akash Levy 3e9a5c68b1 Switch back to main Verific without VHDL support 2026-02-18 21:57:14 -08:00
Akash Levy a9cf998f9f Merge from upstream 2026-01-29 17:46:44 -08:00
Natalia b6c148f84a tests/verific: ensure mixed -f requires VHDL unit 2026-01-28 22:46:10 -08:00
Natalia 5a64fe2d91 tests/verific: assert module count explicitly 2026-01-28 04:21:13 -08:00
Natalia 8c2ef89732 tests/verific: import mixed -f list with -all 2026-01-28 04:13:04 -08:00
Natalia 74c601db0f tests/verific: add mixed -f list case 2026-01-28 03:55:42 -08:00
Akash Levy abd485fa49 Bump Yosys to latest 2025-12-17 21:06:17 -08:00
nataliakokoromyti 2ded4bd893
Update run-test.sh 
fix: preserve newline at eof
 2025-12-16 04:16:03 -08:00
Natalia d4e0437cfd Fix Verific run-test.mk setup 2025-11-24 15:56:28 -08:00
Akash Levy 76c12f8f8c
Merge branch 'YosysHQ:main' into main 2025-11-03 13:38:04 -05:00
Akash Levy 3d06b52ae1 Fix broken Yosys test 2025-10-26 11:40:13 -07:00
Mohamed Gaber dec28f65ae
Merge remote-tracking branch 'donn/pyosys_bugfixes' into merge_pybind11 2025-10-26 02:39:43 +03:00
Robert O'Callahan 25aafab86b Set `port_id` for Verific PortBus wires 2025-10-23 20:51:53 +00:00
Miodrag Milanovic 7d2857b30f Fix regex checks 2025-10-14 16:04:56 +02:00
N. Engelhardt 4513783a02 add tests 2025-10-14 15:48:16 +02:00
Akash Levy 6021168b03 Add back VHDL support 2025-10-02 00:39:33 -07:00
Akash Levy 16215b8786 Merge upstream 2025-09-29 20:58:56 -07:00
Jannis Harder 4bb4b6c662 verific: Extend -sva-continue-on-err to handle FSM explosion 
This also rolls back any added cells and wires, since we might have
added a lot of helper logic by the point we detect this.
 2025-09-27 21:13:02 +02:00
Jannis Harder 83dd99efb7 verific: New `-sva-continue-on-error` import option 
This option allows you to process a design that includes unsupported
SVA. Unsupported SVA gets imported as formal cells using 'x inputs and
with the `unsupported_sva` attribute set. This allows you to get a
complete list of defined properties or to check only a supported subset
of properties. To ensure no properties are unintentionally skipped for
actual verification, even in cases where `-sva-continue-on-error` is
used by default to read and inspect a design, `hierarchy -simcheck` and
`hierarchy -smtcheck` (run by SBY) now ensure that no `unsupported_sva`
property cells remain in the design.
 2025-09-24 18:58:54 +02:00
Akash Levy cc733fd11b Merge from upstream 2025-07-30 22:50:14 -07:00
Robert O'Callahan 8b75c06141 Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
Akash Levy d5f34b5c61 Remove chformal test from verific since it requires initial value preservation 2025-07-21 18:07:49 -07:00
Akash Levy d9fb46b5ac Use a better method of fixing up Verific run-test.mk 2025-07-21 17:08:38 -07:00
Akash Levy 082adf8684
Merge branch 'YosysHQ:main' into main 2025-07-15 00:04:28 -04:00
N. Engelhardt 02323295b0
Merge pull request #5179 from YosysHQ/krys/assert2cover 2025-07-10 14:53:22 +02:00
Akash Levy 3d4bf57745 Merge from upstream 2025-07-02 11:25:18 -07:00
Krystine Sherwin 017524d7a2
tests/verific: Don't ASAN verific 2025-06-28 11:33:18 +12:00
Krystine Sherwin fa68299b25
tests/verific: Add chformal tests 2025-06-14 11:06:38 +12:00
Akash Levy 9cc82c7044 Revert clocking.ys 2025-02-13 20:32:17 -08:00
Akash Levy c8c97ea00b Revert back to using Verific naming 2025-02-13 19:40:33 -08:00
Akash Levy 2ae7490adf Disable Verific blackbox checks (different from our preferred approach) 2025-01-21 05:46:40 -08:00
Akash Levy 53ed83fcac Rename verific to import in tests and update README explanation 2025-01-16 19:34:02 -08:00
Akash Levy 1dcf75d175 Sync 2024-12-19 21:40:30 -08:00
Emil J 6ab5be4a0e
Merge pull request #4814 from YosysHQ/emil/make-test-fasterer 
test: every test everywhere all at once
 2024-12-18 19:02:39 +01:00
Emil J. Tywoniak 6240aec433 test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
Akash Levy 1242db626f Merge remote-tracking branch 'upstream/main' 2024-12-12 22:49:19 -08:00
N. Engelhardt 378864d33b bound attributes: handle vhdl null ranges 2024-12-12 11:42:39 +01:00
N. Engelhardt 03033ab6d4 add more tests for bounds attributes, fix attributes appearing in verilog 2024-12-11 16:11:02 +01:00
Akash Levy e0ba08dd1d
Merge branch 'YosysHQ:main' into main 2024-12-09 11:13:47 -08:00
Akash Levy 8bb193d7c5
Merge branch 'YosysHQ:main' into main 2024-12-08 15:44:46 -08:00
Miodrag Milanovic 05398889ad Add verific verilog test cases for blackboxes 2024-12-06 16:13:25 +01:00
N. Engelhardt 8b0f665cc5 add setenv pass 2024-12-06 11:25:43 +01:00
Akash Levy 3914c21286 verific->import fix for new test case 2024-12-02 20:07:07 -05:00
Akash Levy 6e88c689f2
Merge branch 'YosysHQ:main' into main 2024-12-01 12:32:07 -05:00
Miodrag Milanovic df391f5816 verific: fix blackbox regression and add test case 2024-11-08 14:57:04 +01:00
Akash Levy 2d8588f15b Update Verific 2024-10-02 23:09:36 -07:00
Akash Levy ed2c65314b Standardize convention, add back test, update README 2024-09-23 06:06:43 -07:00
Akash Levy 138228d96e Update Verific README 2024-09-23 05:35:48 -07:00
Akash Levy 0fd6e29e8e Fixups 2024-09-23 04:25:10 -07:00
Akash Levy 2d771a352e Clean up Verific tests 2024-09-23 04:05:08 -07:00