yosys

Commit Graph

Author	SHA1	Message	Date
Miodrag Milanovic	b94b39cd40	Special DP16KD model is required	2025-09-25 15:38:55 +01:00
Ethan Sifferman	0eb93c80e6	added ifndef SIMLIB_NOCONNECT	2025-09-24 20:50:47 -07:00
Emil J. Tywoniak	d30f7847d8	techmap: map $alu to $fa instead of relying on extract_fa	2025-09-23 17:05:12 +02:00
Robert O'Callahan	1e5f920dbd	Remove .c_str() from parameters to log_debug()	2025-09-23 19:10:33 +12:00
Emil J	a78eb9e151	Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort write_rtlil: don't sort	2025-09-22 11:14:39 +02:00
YRabbit	d60dc93e92	Gowin. Renaming inputs of the DCS primitive. The dynamic clock selection (DCS) primitive has undergone changes with the release of the GW5A series—the CLK0,1,2,3 inputs are now CLKIN0,1,2,3, but only for GW5A series chips. There are no functional changes, only renaming. Here we are transferring the description of the DCS primitive from general to specialized files for each chip series. We have also fixed a bug in the generation script that caused the loss of primitive parameters. Fortunately, this only affected the analog-to-digital converter, which has not yet been implemented. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>	2025-09-20 16:22:23 +01:00
Jannis Harder	1251e92e3a	Add `$input_port` and `$connect` cell types	2025-09-17 13:56:46 +02:00
Robert O'Callahan	a7c46f7b4a	Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix()	2025-09-16 23:02:16 +00:00
Robert O'Callahan	5ac6858f26	Remove .c_str() from log_cmd_error() and log_file_error() parameters	2025-09-16 22:59:08 +00:00
Emil J. Tywoniak	73747f6928	read_verilog: add -relativeshare for synthesis reproducibility testing	2025-09-16 15:47:35 +02:00
Robert O'Callahan	1a367b907c	Use fast path for 32-bit Const integer constructor in more places	2025-09-16 03:17:24 +00:00
Robert O'Callahan	09b493cfcd	Update techlibs to avoid bits()	2025-09-16 03:17:23 +00:00
Robert O'Callahan	e0ae7b7af4	Remove .c_str() calls from log()/log_error() There are some leftovers, but this is an easy regex-based approach that removes most of them.	2025-09-11 20:59:37 +00:00
Robert O'Callahan	c7df6954b9	Remove .c_str() from stringf parameters	2025-09-01 23:34:42 +00:00
N. Engelhardt	15d24bf2e6	synth_quicklogic: add -noflatten option	2025-08-25 17:25:58 +02:00
Miodrag Milanović	c7e6275d0d	Merge pull request #5045 from danderson/push-nwpulrqymkqp techlibs/lattice: add missing clock muxes to ECP5 block ram blackboxes	2025-08-25 15:28:34 +02:00
Robert O'Callahan	8b75c06141	Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.	2025-07-22 10:38:38 +00:00
Martin Povišer	9ab1946799	Merge pull request #5209 from povik/hieropt Start `opt_hier` to enable hierarchical optimization	2025-07-17 14:12:18 +02:00
Martin Povišer	415b7d3f65	Drop experimental label off `synth -hieropt`	2025-07-17 12:02:44 +02:00
Martin Povišer	22a44e4333	Start `opt_hier`	2025-07-05 16:45:52 +02:00
YRabbit	85e7c68fc6	Gowin. BUGFIX. Fix multi-line descriptions. If let's say the enumeration of inputs took several lines, then all after the first one were ignored. Since the first line ended with a comma, an error was generated when trying to use the resulting file. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>	2025-07-02 12:39:18 +10:00
KrystalDelusion	5268565410	Merge pull request #5108 from marzoul/adrien-uram Create a single-port URAM mapping to support memories 2048 x 144b	2025-05-13 09:54:36 +12:00
Adrien Prost-Boucle	6bf7587338	URAM mapping : Add test for 2048 x 144b	2025-05-10 14:53:56 +02:00
Adrien Prost-Boucle	c7de531231	URAM mapping : Fix port indexes according to Yosys warnings	2025-05-09 15:09:11 +02:00
Adrien Prost-Boucle	c4a49f0c55	Create a single-port URAM mapping to support memories 2048 x 144b	2025-05-09 14:16:03 +02:00
Patrick Urban	6d575918fc	gatemate: Set unused BRAM inputs to 'bx This will reduce the number of CPEs to generate fixed values at the block RAM inputs, if it is not used.	2025-04-28 14:42:16 +02:00
KrystalDelusion	2d6255175e	Merge pull request #5057 from secworks/blocking_assignment_greenpak4_cells_sim_digital Change to use blocking assignments in non-clocked processes.	2025-04-26 11:15:10 +12:00
KrystalDelusion	6564810ae3	Merge pull request #4992 from Anhijkt/fix-ice40dsp-unsigned ice40_dsp: fix const handling	2025-04-26 11:15:02 +12:00
Miodrag Milanović	febc07e6fb	Merge pull request #5039 from YosysHQ/gatemate_bram gatemate: WRITE_THROUGH mode change	2025-04-25 09:53:43 +02:00
Emil J	f8c027b70e	Merge pull request #5056 from secworks/blocking_assignment_gatemate_cells_sim Change to blocking assignments in non-clocked process.	2025-04-23 23:13:54 +02:00
Joachim Strömbergson	2fcb61adb5	Change to use blocking assignments in non-clocked processes. Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2025-04-23 17:21:32 +02:00
Joachim Strömbergson	90f50722ab	Change to blocking assignments in non-clocked process. Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2025-04-23 17:13:37 +02:00
Joachim Strömbergson	e4d6781088	Changing non clocked alway assignment to blocking. Signed-off-by: Joachim Strömbergson <joachim@assured.se>	2025-04-23 16:59:53 +02:00
David Anderson	af8e85b7d2	techlibs/lattice: add missing clock muxes to ECP5 block ram blackboxes prjtrellis documentation shows that EBR clock inputs have optional inverters. The bram techmap outputs those parameters, and nextpnr consumes them. But for whatever reason, Diamond doesn't include those parameters in its blackbox models. This makes synth_lattice fail when targeting ECP5 with a design that maps block RAMs if you include any pass that needs cells_bb_ecp5.v's definitions. This change fixes up the ECP5 bram blackbox models at generation time, by adding the missing parameters back in. Signed-off-by: David Anderson <dave@natulte.net>	2025-04-21 11:57:49 -07:00
Miodrag Milanovic	c343462c16	gatemate: WRITE_THROUGH mode change	2025-04-18 14:16:02 +02:00
Anhijkt	163e339c69	ice40_dsp: add unextend_unsigned function	2025-04-11 19:41:35 +03:00
Anhijkt	4a178d7cff	ice40_dsp: change unextend call condition	2025-04-10 17:42:39 +03:00
Adrien Prost-Boucle	3911a627a8	Clearer diff for the all-x corner case	2025-04-07 07:55:30 +02:00
Adrien Prost-Boucle	7a1729e609	Fix mux xilinx mapping when all inputs are x	2025-04-06 11:43:17 +02:00
Anhijkt	2b3a148fc4	ice40_dsp: fix const handling	2025-04-05 13:46:38 +03:00
Emil J	1b25e1cee0	Merge pull request #4942 from Anhijkt/fix-ice40dsp ice40_dsp: fix log_assert issue	2025-03-28 13:32:17 +01:00
YRabbit	c37db637c7	Gowin. Remove unnecessary modules Primitives that are not planned for implementation for reasons of belonging to old unsupported chips or representing composite complex IPs rather than primitives are removed. Also latches and large MUXes not planned for implementation. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>	2025-03-28 06:34:26 +10:00
Scott Ashcroft	04bbd4e7e2	Make all vector-size related integer params in $print sim model signed This fixes iverilog crashes on 32-bit, similar to `95944eb` for $mem.	2025-03-25 13:08:49 +00:00
Miodrag Milanović	733487e730	Merge pull request #4950 from pu-cc/gatemate-serdes-update gatemate: Add `CC_SERDES` parameters and update port names	2025-03-20 10:52:23 +01:00
Anhijkt	a9d765e11e	ice40_dsp: group empty wires	2025-03-16 15:11:45 +02:00
Anhijkt	725c489c7e	ice40_dsp: fix log_assert issue	2025-03-15 17:11:32 +02:00
Martin Povišer	6da543a61a	Merge pull request #4818 from povik/macc_v2 Add `$macc_v2`	2025-03-12 22:55:40 +01:00
KrystalDelusion	bf96ed322d	Merge pull request #4827 from aerkiaga/main Update ALU MULT mode in gowin to match nextpnr	2025-03-13 10:49:37 +13:00
Martin Povišer	d8a4991289	Merge pull request #4931 from povik/buf-clean opt_clean, simplemap: Add `$buf` handling	2025-03-10 15:10:17 +01:00
Martin Povišer	9f7cdd4bd4	Merge pull request #4262 from RoaLogic/master MAX10 updates	2025-03-07 19:59:55 +01:00
Martin Povišer	557047fe1e	opt_clean, simplemap: Add `$buf` handling	2025-03-07 16:08:38 +01:00
N. Engelhardt	268a034b21	Merge pull request #4866 from YosysHQ/ql_ioff add IOFF inference for qlf_k6n10f	2025-03-03 14:12:09 +00:00
N. Engelhardt	303a386ecc	create duplicate IOFFs if multiple output ports are connected to the same register	2025-01-31 11:28:57 +01:00
Krystine Sherwin	0ec5f1b756	pmgen: Move passes out of pmgen folder - Techlib pmgens are now in relevant techlibs/. - `peepopt` pmgens are now in passes/opt. - `test_pmgen` is still in passes/pmgen. - Update `Makefile.inc` and `.gitignore` file(s) to match new `_pm.h` location, as well as the `#include`s. - Change default `%_pm.h` make target to `techlibs/%_pm.h` and move it to the top level Makefile. - Update pmgen target to use `$(notdir $)` (where `$` is the part of the file name that matched the '%' in the target) instead of `$(subst _pm.h,,$(notdir $@))`.	2025-01-31 15:18:28 +13:00
N. Engelhardt	25b400982b	detect aliased I/O ports	2025-01-28 17:37:23 +01:00
N. Engelhardt	9da4fe747e	fix bus ioff inference	2025-01-28 11:23:36 +01:00
Martin Povišer	6c76dcec3e	macc_v2: Fix v2 omissions	2025-01-27 13:08:44 +01:00
N. Engelhardt	1cf8e7c7db	add ioff inference for qlf_k6n10f	2025-01-24 21:17:15 +01:00
Martin Povišer	3184b335da	macc_v2: Fix language constructs in simlib model	2025-01-24 13:22:30 +01:00
Martin Povišer	1e8aa56f7f	macc_v2: Init simlib model	2025-01-24 12:38:03 +01:00
Emil J. Tywoniak	a58481e9b7	mark all hash_into methods nodiscard	2025-01-14 12:39:15 +01:00
Emil J	9f7040b3d1	Merge pull request #4683 from keszybz/use-SOURCE_DATE_EPOCH Respect $SOURCE_DATE_EPOCH in generate_bram_types_sim.py	2025-01-10 23:43:26 +01:00
Patrick Urban	1fdb2a4511	gatemate: Add `CC_SERDES` parameters and update port names	2025-01-10 10:25:10 +01:00
Aritz Erkiaga	9a11204329	Update ALU MULT mode in gowin to match nextpnr	2024-12-23 11:12:48 +01:00
Emil J. Tywoniak	b9b9515bb0	hashlib: hash_eat -> hash_into	2024-12-18 15:09:25 +01:00
Emil J. Tywoniak	4e29ec1854	hashlib: acc -> eat	2024-12-18 15:09:25 +01:00
Emil J. Tywoniak	d071489ab1	hashlib: redo interface for flexibility	2024-12-18 14:49:25 +01:00
Miodrag Milanović	f4ddbc3994	Merge pull request #4771 from pepijndevos/famxtra gowin: split cells_xtra by family	2024-12-08 19:46:36 +01:00
KrystalDelusion	c96d02b204	Merge pull request #4784 from YosysHQ/krys/reduce_warnings Reduce number of warnings	2024-12-05 09:16:06 +13:00
Emil J	61a6567b9f	Merge pull request #4789 from YosysHQ/emil/sklansky-adder Add a Sklansky option for `$lcu` mapping	2024-12-03 11:33:13 +01:00
Emil J. Tywoniak	fe64a714a9	techmap: add a Sklansky option for `$lcu` mapping	2024-12-02 11:34:58 +01:00
Emil J. Tywoniak	ebd7f2b366	techlibs: add _TECHMAP_DO_ to Han-Carlson adder	2024-12-02 09:54:24 +01:00
Krystine Sherwin	1de5d98ae2	Reduce comparisons of size_t and int `Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`. For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.	2024-11-29 12:53:29 +13:00
Emil J. Tywoniak	4bf3677640	techmap: set Han-Carlson adder priority consistent with Kogge-Stone	2024-11-28 23:54:00 +01:00
Emil J. Tywoniak	6c78bd3637	techmap: add a Han-Carlson option for `$lcu` mapping	2024-11-28 15:33:21 +01:00
Pepijn de Vos	be836f4af3	gowin: split cells_xtra by family	2024-11-26 15:42:22 +01:00
Emil J	88abc4c20f	Merge pull request #4755 from pepijndevos/cells_xtra Gowin: add GW2A and GW5A cells	2024-11-20 13:32:30 +01:00
Pepijn de Vos	b8329df1d0	add GW2A and GW5A cells	2024-11-17 20:25:11 +01:00
Patrick Urban	77e1f748a5	gatemate: run `simplemap` after `muxcover` to prevent unmapped multiplexers	2024-11-15 09:49:49 +01:00
Zbigniew Jędrzejewski-Szmek	26a3478d8d	Drop timestamp in generate_bram_types_sim.py I'm working on build reproducibility of Fedora packages, and this patch fixes an issue observed in test rebuilds: the timestamp was set to the actual time of the build, making builds nonreproducible. Other "Generated by" strings do not include a timestamp, so drop it here too.	2024-10-30 08:47:18 +01:00
Krystine Sherwin	27b8b4e81e	Docs: Fix missing groups $lut and $sop were missed in the rebase, and $buf is new to main since the last rebase.	2024-10-15 11:08:30 +13:00
Krystine Sherwin	1513366f21	Docs: Adding mux cell descriptions Also making ver2 cell descriptions consistently spaced.	2024-10-15 07:37:34 +13:00
Krystine Sherwin	dfe803b5c6	Docs: Comments from @jix - Unswap shift/shiftx - Add brief overview to cell lib - Clarify $div cell B input - Clarify unary operators - What is $modfloor	2024-10-15 07:37:20 +13:00
Krystine Sherwin	4d84d7e69f	simlib.v: Add x-output tag Also a few extra cell help texts.	2024-10-15 07:35:41 +13:00
Krystine Sherwin	ed92374263	simlib.v: Update case equality operators to v2 Also tag as x-aware cells and add titles.	2024-10-15 07:35:41 +13:00
Krystine Sherwin	b1025dbaa6	cellhelp.py: Cells can have tags Tags are added to the list of properties when exporting to `cells.json`.	2024-10-15 07:35:41 +13:00
Krystine Sherwin	f70a66f5b3	Docs: Assert cell has group Explicitly assign $_TBUF_ to `gate_other` and remove catch if a cell has no group.	2024-10-15 07:35:40 +13:00
Krystine Sherwin	5c4f7b4deb	Docs: $eqx aka case equality	2024-10-15 07:35:40 +13:00
Krystine Sherwin	596d914ead	simcells: Apply group tags	2024-10-15 07:35:40 +13:00
Krystine Sherwin	78b9dbd4ea	Docs: Assign remaining word cells to groups Move todos to correct place. Add todo for x-prop cells.	2024-10-15 07:35:40 +13:00
Krystine Sherwin	1374fc2e2b	cellref: Deprecate cell_library.rst Most of the word/coarse level cells have an assigned group and individual page. The gate/fine level cells are all on one page. Fix links to `cell_library.rst`.	2024-10-15 07:34:52 +13:00
Krystine Sherwin	04b0ae540d	cellref: Move default help message to register.cc Drop the default help message from rst while still displaying it on the command line. Fix command line formatting for older style help messages.	2024-10-15 07:31:47 +13:00
Krystine Sherwin	c662529316	Docs: Move binary operators to cell appendix Add binary group tag to relevant cells. Remove content from `cell_library.rst` that is already moved.	2024-10-15 07:31:47 +13:00
Krystine Sherwin	7c5b10fe50	cellref: Add json dump New `help -dump-cells-json <file>` to dump cells list. Add 'group' field to SimHelper class/struct with defaults to gate_other and word_other depending on source (simcells or simlib). Add 'unary' group to unary operator cells for testing (based on internal cell library docs page).	2024-10-15 07:25:27 +13:00
Krystine Sherwin	06e5e18371	simlib.v: Autolink referenced cells in alu	2024-10-15 07:23:45 +13:00
Krystine Sherwin	21747c468c	Docs: Improve cell_help usage - Drop `cell_code` and instead map code lookups to the `cell_help` dict. - Add helper functions to struct for checking and getting the right cell. - Add `CellType` for cell to `write_cell_rst` function declaration in preparation for use in future. - Iterate over `yosys_celltypes.cell_types` when exporting cell rst files, reporting errors for any cells defined in `cell_types` but not `cell_help_messages`.	2024-10-15 07:23:45 +13:00
Krystine Sherwin	57cd8d29db	cellhelp: Add default format parse for simcells Since `simcells.v` uses consistent formatting we can handle it specifically to help tidy up sphinx warnings about the truth tables, and instead chuck them in a code block which when printing to rst. Also has the side effect that rst code blocks can be added manually with `//- ::` followed by a blank line.	2024-10-15 07:16:40 +13:00
Krystine Sherwin	a2b2904ed8	cellhelp: Add source line to help Include Source file and line number in SimHelper struct, and use it for verilog code caption in rst dump. Also reformat python string conversion to iterate over a list of fields instead of repeating code for each.	2024-10-15 07:16:40 +13:00
Krystine Sherwin	784292626e	cellhelp: Rename short_desc to title	2024-10-15 07:16:39 +13:00
Krystine Sherwin	4662476ec8	Docs: Test $alu with v2 help format	2024-10-15 07:16:39 +13:00

1 2 3 4 5 ...

2538 Commits