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2488 Commits

Author SHA1 Message Date
Ethan Sifferman d5beb65d30 added SIMLIB_VERILATOR_COMPAT 2025-10-01 10:19:25 -07:00
Ethan Sifferman 0eb93c80e6 added ifndef SIMLIB_NOCONNECT 2025-09-24 20:50:47 -07:00
Emil J. Tywoniak d30f7847d8 techmap: map $alu to $fa instead of relying on extract_fa 2025-09-23 17:05:12 +02:00
Robert O'Callahan 1e5f920dbd Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
Emil J a78eb9e151
Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort 
write_rtlil: don't sort
 2025-09-22 11:14:39 +02:00
YRabbit d60dc93e92 Gowin. Renaming inputs of the DCS primitive. 
The dynamic clock selection (DCS) primitive has undergone changes with
the release of the GW5A series—the CLK0,1,2,3 inputs are now
CLKIN0,1,2,3, but only for GW5A series chips.

There are no functional changes, only renaming.

Here we are transferring the description of the DCS primitive from
general to specialized files for each chip series.

We have also fixed a bug in the generation script that caused the loss
of primitive parameters. Fortunately, this only affected the
analog-to-digital converter, which has not yet been implemented.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-09-20 16:22:23 +01:00
Jannis Harder 1251e92e3a Add `$input_port` and `$connect` cell types 2025-09-17 13:56:46 +02:00
Robert O'Callahan a7c46f7b4a Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix() 2025-09-16 23:02:16 +00:00
Robert O'Callahan 5ac6858f26 Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
Emil J. Tywoniak 73747f6928 read_verilog: add -relativeshare for synthesis reproducibility testing 2025-09-16 15:47:35 +02:00
Robert O'Callahan 1a367b907c Use fast path for 32-bit Const integer constructor in more places 2025-09-16 03:17:24 +00:00
Robert O'Callahan 09b493cfcd Update techlibs to avoid bits() 2025-09-16 03:17:23 +00:00
Robert O'Callahan e0ae7b7af4 Remove .c_str() calls from log()/log_error() 
There are some leftovers, but this is an easy regex-based approach that removes most of them.
 2025-09-11 20:59:37 +00:00
Robert O'Callahan c7df6954b9 Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00
N. Engelhardt 15d24bf2e6 synth_quicklogic: add -noflatten option 2025-08-25 17:25:58 +02:00
Miodrag Milanović c7e6275d0d
Merge pull request #5045 from danderson/push-nwpulrqymkqp 
techlibs/lattice: add missing clock muxes to ECP5 block ram blackboxes
 2025-08-25 15:28:34 +02:00
Robert O'Callahan 8b75c06141 Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
Martin Povišer 9ab1946799
Merge pull request #5209 from povik/hieropt 
Start `opt_hier` to enable hierarchical optimization
 2025-07-17 14:12:18 +02:00
Martin Povišer 415b7d3f65 Drop experimental label off `synth -hieropt` 2025-07-17 12:02:44 +02:00
Martin Povišer 22a44e4333 Start `opt_hier` 2025-07-05 16:45:52 +02:00
YRabbit 85e7c68fc6 Gowin. BUGFIX. Fix multi-line descriptions. 
If let's say the enumeration of inputs took several lines, then all
after the first one were ignored. Since the first line ended with a
comma, an error was generated when trying to use the resulting file.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-07-02 12:39:18 +10:00
KrystalDelusion 5268565410
Merge pull request #5108 from marzoul/adrien-uram 
Create a single-port URAM mapping to support memories 2048 x 144b
 2025-05-13 09:54:36 +12:00
Adrien Prost-Boucle 6bf7587338 URAM mapping : Add test for 2048 x 144b 2025-05-10 14:53:56 +02:00
Adrien Prost-Boucle c7de531231 URAM mapping : Fix port indexes according to Yosys warnings 2025-05-09 15:09:11 +02:00
Adrien Prost-Boucle c4a49f0c55 Create a single-port URAM mapping to support memories 2048 x 144b 2025-05-09 14:16:03 +02:00
Patrick Urban 6d575918fc gatemate: Set unused BRAM inputs to 'bx 
This will reduce the number of CPEs to generate fixed values at the block RAM inputs, if it is not used.
 2025-04-28 14:42:16 +02:00
KrystalDelusion 2d6255175e
Merge pull request #5057 from secworks/blocking_assignment_greenpak4_cells_sim_digital 
Change to use blocking assignments in non-clocked processes.
 2025-04-26 11:15:10 +12:00
KrystalDelusion 6564810ae3
Merge pull request #4992 from Anhijkt/fix-ice40dsp-unsigned 
ice40_dsp: fix const handling
 2025-04-26 11:15:02 +12:00
Miodrag Milanović febc07e6fb
Merge pull request #5039 from YosysHQ/gatemate_bram 
gatemate: WRITE_THROUGH mode change
 2025-04-25 09:53:43 +02:00
Emil J f8c027b70e
Merge pull request #5056 from secworks/blocking_assignment_gatemate_cells_sim 
Change to blocking assignments in non-clocked process.
 2025-04-23 23:13:54 +02:00
Joachim Strömbergson 2fcb61adb5
Change to use blocking assignments in non-clocked processes. 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2025-04-23 17:21:32 +02:00
Joachim Strömbergson 90f50722ab
Change to blocking assignments in non-clocked process. 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2025-04-23 17:13:37 +02:00
Joachim Strömbergson e4d6781088
Changing non clocked alway assignment to blocking. 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2025-04-23 16:59:53 +02:00
David Anderson af8e85b7d2 techlibs/lattice: add missing clock muxes to ECP5 block ram blackboxes 
prjtrellis documentation shows that EBR clock inputs have optional inverters.
The bram techmap outputs those parameters, and nextpnr consumes them. But for
whatever reason, Diamond doesn't include those parameters in its blackbox
models. This makes synth_lattice fail when targeting ECP5 with a design that
maps block RAMs if you include any pass that needs cells_bb_ecp5.v's definitions.

This change fixes up the ECP5 bram blackbox models at generation time, by
adding the missing parameters back in.

Signed-off-by: David Anderson <dave@natulte.net>
 2025-04-21 11:57:49 -07:00
Miodrag Milanovic c343462c16 gatemate: WRITE_THROUGH mode change 2025-04-18 14:16:02 +02:00
Anhijkt 163e339c69 ice40_dsp: add unextend_unsigned function 2025-04-11 19:41:35 +03:00
Anhijkt 4a178d7cff ice40_dsp: change unextend call condition 2025-04-10 17:42:39 +03:00
Adrien Prost-Boucle 3911a627a8 Clearer diff for the all-x corner case 2025-04-07 07:55:30 +02:00
Adrien Prost-Boucle 7a1729e609 Fix mux xilinx mapping when all inputs are x 2025-04-06 11:43:17 +02:00
Anhijkt 2b3a148fc4 ice40_dsp: fix const handling 2025-04-05 13:46:38 +03:00
Emil J 1b25e1cee0
Merge pull request #4942 from Anhijkt/fix-ice40dsp 
ice40_dsp: fix log_assert issue
 2025-03-28 13:32:17 +01:00
YRabbit c37db637c7 Gowin. Remove unnecessary modules 
Primitives that are not planned for implementation for reasons of
belonging to old unsupported chips or representing composite complex IPs
rather than primitives are removed.
Also latches and large MUXes not planned for implementation.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-03-28 06:34:26 +10:00
Scott Ashcroft 04bbd4e7e2 Make all vector-size related integer params in $print sim model signed 
This fixes iverilog crashes on 32-bit, similar to 95944eb for $mem.
 2025-03-25 13:08:49 +00:00
Miodrag Milanović 733487e730
Merge pull request #4950 from pu-cc/gatemate-serdes-update 
gatemate: Add `CC_SERDES` parameters and update port names
 2025-03-20 10:52:23 +01:00
Anhijkt a9d765e11e ice40_dsp: group empty wires 2025-03-16 15:11:45 +02:00
Anhijkt 725c489c7e ice40_dsp: fix log_assert issue 2025-03-15 17:11:32 +02:00
Martin Povišer 6da543a61a
Merge pull request #4818 from povik/macc_v2 
Add `$macc_v2`
 2025-03-12 22:55:40 +01:00
KrystalDelusion bf96ed322d
Merge pull request #4827 from aerkiaga/main 
Update ALU MULT mode in gowin to match nextpnr
 2025-03-13 10:49:37 +13:00
Martin Povišer d8a4991289
Merge pull request #4931 from povik/buf-clean 
opt_clean, simplemap: Add `$buf` handling
 2025-03-10 15:10:17 +01:00
Martin Povišer 9f7cdd4bd4
Merge pull request #4262 from RoaLogic/master 
MAX10 updates
 2025-03-07 19:59:55 +01:00