16 Commits

Author	SHA1	Message	Date
Akash Levy	a705042d2e	Merge branch 'YosysHQ:main' into main	2025-11-20 23:05:40 -05:00
Emil J. Tywoniak	9e81db4373	ff: split out type-only information	2025-11-19 15:20:50 +01:00
Akash Levy	60d969530b	Bump to latest	2025-09-21 01:10:04 -07:00
Robert O'Callahan	6dc9a8bacf	Update kernel to avoid bits()	2025-09-16 03:17:23 +00:00
Akash Levy	52a1493548	Naming improvements	2024-11-21 03:29:35 -08:00
Akash Levy	bbbc292209	Smallfixes	2024-11-20 21:10:58 -08:00
Akash Levy	08ff023510	Naming fix for ff.cc	2024-11-20 20:59:04 -08:00
Akash Levy	469f5a707a	Merge branch 'YosysHQ:main' into main	2024-10-14 11:21:54 -07:00
Emil J. Tywoniak	785bd44da7	rtlil: represent Const strings as std::string	2024-10-14 06:28:12 +02:00
Akash Levy	dd487ca8a1	Updating Yosys	2024-10-03 01:46:09 -07:00
Akash Levy	f7ffd73fa0	Fix opt_dff problem	2024-08-01 09:20:18 -07:00
Akash Levy	187737b86a	Don't adjust naming on imported cells. Add $ for each pass	2024-05-19 15:02:40 -07:00
Jannis Harder	c0063288d6	Add the $anyinit cell and the formalff pass ... These can be used to protect undefined flip-flop initialization values from optimizations that are not sound for formal verification and can help mapping all solver-provided values in witness traces for flows that use different backends simultaneously.	2022-08-16 13:37:30 +02:00
Marcelina Kościelnicka	2858bb03cd	Add opt_ffinv pass.	2022-05-13 23:02:30 +02:00
Marcelina Kościelnicka	0a0df8d38c	dfflegalize: Refactor, add aldff support.	2021-10-27 14:14:01 +02:00
Marcelina Kościelnicka	4e70c30775	FfData: some refactoring. ... - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases	2021-10-07 04:24:06 +02:00