yosys

Author	SHA1	Message	Date
Miodrag Milanovic	a689342207	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
Krystine Sherwin	c3ffb48a6b	Add and use fix_mod.py	2026-01-28 07:45:58 +13:00
YRabbit	d60dc93e92	Gowin. Renaming inputs of the DCS primitive. The dynamic clock selection (DCS) primitive has undergone changes with the release of the GW5A series—the CLK0,1,2,3 inputs are now CLKIN0,1,2,3, but only for GW5A series chips. There are no functional changes, only renaming. Here we are transferring the description of the DCS primitive from general to specialized files for each chip series. We have also fixed a bug in the generation script that caused the loss of primitive parameters. Fortunately, this only affected the analog-to-digital converter, which has not yet been implemented. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>	2025-09-20 16:22:23 +01:00
YRabbit	c37db637c7	Gowin. Remove unnecessary modules Primitives that are not planned for implementation for reasons of belonging to old unsupported chips or representing composite complex IPs rather than primitives are removed. Also latches and large MUXes not planned for implementation. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>	2025-03-28 06:34:26 +10:00
Pepijn de Vos	be836f4af3	gowin: split cells_xtra by family	2024-11-26 15:42:22 +01:00