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7,589 Commits 111 Branches 62 Tags 55 MiB
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8 Commits

Author SHA1 Message Date
Miodrag Milanovic 03a3deec43 Cleanup and formating 2019-10-04 11:09:59 +02:00
Miodrag Milanovic a5844e3ceb split latches into separate checks 2019-10-04 11:08:42 +02:00
Miodrag Milanovic 3238ee7d35 check muxes per type 2019-10-04 11:04:18 +02:00
Miodrag Milanovic 91ad3ab717 check ff's separately 2019-10-04 11:00:49 +02:00
Miodrag Milanovic 3d3479b0af Cleanup top modules and not used defines 2019-10-04 10:57:47 +02:00
Miodrag Milanovic 1435b9bf97 remove alu test 2019-10-04 10:55:13 +02:00
Sergey fc56459746
run-test.sh Move $x at end of line. 2019-10-01 10:55:34 +03:00
SergeyDegtyar 27377c4663 Add new tests for Anlogic architecture 
Problems/questions:
	- memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type
EG_LOGIC_DRAM16X4) to SAT database.
		Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM?
	- Internal cell type $_TBUF_  is present.
 2019-09-23 12:12:02 +03:00