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15779 Commits

Author SHA1 Message Date
Robert O'Callahan e0e70d1158 Remove some `c_str()` calls where they're no longer needed as parameters to `stringf()`. 2025-08-18 14:20:31 +01:00
Emil J f0ccc65820
Merge pull request #5297 from rocallahan/redundant-assignmap 
Remove redundant construction of `assign_map`.
 2025-08-18 10:43:44 +02:00
Miodrag Milanović 1a52a714b4
Merge pull request #5280 from YosysHQ/krys/ci_changes 
Workflow adjustments
 2025-08-18 10:17:12 +02:00
github-actions[bot] d73cd78001 Bump version 2025-08-18 00:27:23 +00:00
Robert O'Callahan 3f2c4f6f83 Remove redundant construction of `assign_map`. 
We call 'assign_map.set()' below which wipes the `SigMap` and reconstructs it.

This operation is expensive because it scans the whole module. I think it's
better to make heavyweight operations more visible so I'm removing
the less obvious operation.
 2025-08-17 23:34:11 +00:00
KrystalDelusion 6d55ca204b
Merge pull request #5281 from suisseWalter/add_parameterised_cells_stat 
STAT: Add parameterised cells
 2025-08-18 09:21:45 +12:00
clemens 9278bed853 removed copyright notice on lib file. 
Should be covered by the yosys license not  anything else.
 2025-08-16 09:40:03 +02:00
clemens 4e45b5e1bb permit trailing comma 2025-08-16 09:40:03 +02:00
clemens 73d1177665 testcases 
one testcase for single parameter cells.
one testcase for double parameter cells.
 2025-08-16 09:40:03 +02:00
clemens 8b1f77ebd2 cleanup. printf to errors or warnings 2025-08-16 09:40:03 +02:00
clemens 50fe9dd7f2 clean parsing code 2025-08-16 09:40:03 +02:00
clemens 5fc0e77c3d add functionality to be able to use parameterised cells. 
cells can have their area as a function of the input port width.
 2025-08-16 09:40:03 +02:00
clemens d8fb4da437 updated testcase 2025-08-16 09:32:08 +02:00
clemens a6e0ab5ea5 Update (sequential) area to be only local without -hierarchy 2025-08-16 09:09:57 +02:00
suisseWalter f5b219f59e
Update passes/cmds/stat.cc 
Co-authored-by: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com>
 2025-08-16 08:36:06 +02:00
github-actions[bot] d10fdc0ec5 Bump version 2025-08-16 00:24:02 +00:00
KrystalDelusion 7799c6e6ac
Merge pull request #5291 from YosysHQ/krys/rename_escape 
rename.cc: Fixup ports after -unescape
 2025-08-16 12:19:49 +12:00
Robert O'Callahan e906ea3f1b Add tests for dynamic precision and with with an int parameter 2025-08-15 23:58:58 +00:00
KrystalDelusion 4a324e1da8
Merge pull request #5292 from rocallahan/wasm-varargs 
Fix vararg alignment
 2025-08-16 10:29:36 +12:00
Emil J 70600bb596
Merge pull request #5239 from rocallahan/abc-incremental 
In the ABC pass, avoid scanning the entire module for each ABC run
 2025-08-15 20:17:32 +02:00
Robert O'Callahan 6d62a1fff7 Fix vararg alignment 2025-08-15 05:43:53 +00:00
github-actions[bot] bf625951d7 Bump version 2025-08-15 00:26:03 +00:00
Robert O'Callahan dd88423334 Make OptMuxtree int-indexed vectors into hashtables 
For one of our large circuits, this reduced the time for an OPT_MUXTREE pass from
169s to 5s.
 2025-08-14 23:09:15 +00:00
Krystine Sherwin ec18d1aede
rename.cc: Fixup ports after -unescape 2025-08-15 10:48:32 +12:00
Robert O'Callahan 62c441107d Build FfInitVals for the entire module once and use it for every ABC run. 2025-08-14 22:29:51 +00:00
Robert O'Callahan 2654bd5355 Compute `is_port` in AbcPass without iterating through all cells and wires in the module every time we run ABC. 
This does not scale when we run ABC thousands of times in a single AbcPass.
 2025-08-14 22:29:45 +00:00
Robert O'Callahan ac8259b02e Preserve `assign_map` across ABC invocations. 
Currently `assign_map` is rebuilt from the module from scratch every time we invoke ABC.
That doesn't scale when we do thousands of ABC runs over large modules. Instead,
create it once and then maintain incrementally it as we update the module.
 2025-08-14 22:27:04 +00:00
Robert O'Callahan 4de3ee093e Mark kept FF output wires as ports directly instead of via the 'keep' attribute 2025-08-14 22:26:38 +00:00
Emil J 195d3ef940
Merge pull request #5100 from jix/rename_move_to_cell 
rename: add -move-to-cell option in -wire mode
 2025-08-14 16:45:33 +02:00
Miodrag Milanovic 1dbf2df983 Add libfl-dev for CodeQL CI job 2025-08-14 09:15:43 +02:00
github-actions[bot] a265b23ac0 Bump version 2025-08-14 00:25:16 +00:00
Anhijkt e486994f60 opt_dff: add test 2025-08-14 00:13:23 +03:00
clemens 71307b4a51 add Testcases 
Fix existing testcases
Fix edgecase where modules where counted as cells.
 2025-08-13 14:46:01 +02:00
Emil J dbb977aa8b
Merge pull request #5288 from YosysHQ/emil/demote-verilog-parser-errors-again 
verilog: demote some parser errors to warnings again
 2025-08-13 12:52:50 +02:00
Emil J. Tywoniak 856fc43a87 rename: format vector slices consistently with HDL upto/downto direction 2025-08-13 11:11:53 +02:00
Jannis Harder 77089a8d03 rename: add -move-to-cell option in -wire mode 2025-08-13 11:11:52 +02:00
Emil J. Tywoniak 1603828b30 verilog_parser: fix locations of warnings for restrict keyword 2025-08-13 10:56:48 +02:00
Emil J. Tywoniak 910ff3ff36 verilog: demote some parser errors to warnings again 2025-08-13 10:54:47 +02:00
clemens 383d11c2ac fix design overview in json. 
Fix some unknown cells apearing twice.
 2025-08-13 10:09:02 +02:00
clemens 1eb8844e38 fix labeling in report 
fix design hierarchy containing wrong values.
remove left over debug print.
 2025-08-13 08:36:26 +02:00
Robert O'Callahan ccb23ffc1a Fix indentation 2025-08-13 05:44:52 +00:00
Robert O'Callahan 885bb744e3 Make `module` a parameter of the function so we can change its constness in context 2025-08-13 05:44:52 +00:00
Robert O'Callahan 53c72c0d39 Move code in `abc_module()` that modifies the design into a new function `extract()` 
Splits up the big `abc_module()` function and isolates the code that modifies the design
after running ABC.
 2025-08-13 05:44:52 +00:00
Robert O'Callahan ceedcecfae Move the input parameters to `abc_module` that are identical across modules to an `AbcConfig` struct. 2025-08-13 05:44:52 +00:00
Robert O'Callahan 4ba42c4752 Move ABC pass state to a struct instead of storing it in global variables. 2025-08-13 05:44:52 +00:00
github-actions[bot] 8634d83320 Bump version 2025-08-13 00:25:15 +00:00
Anhijkt b3ca5ee0f1 opt_dff: fix timeout issue 2025-08-13 01:48:59 +03:00
Jannis Harder 1f876f3a22 abstract: Add -initstates option 2025-08-12 15:37:12 +02:00
Jannis Harder 256aa3e389 check: Limit detailed cell edge checking for $pmux and $bmux 
While these cells can't have a quadratic number of edges between A, B
and Y, they do have a quadratic number of edges between S and Y.
 2025-08-12 14:38:20 +02:00
Emil J 9d047f9a30
Merge pull request #5283 from YosysHQ/emil/fix-simplify-initstate 
simplify: fix initstate crash
 2025-08-12 14:28:31 +02:00