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2213 Commits

Author SHA1 Message Date
Krystine Sherwin f9e8127e2b
tests: Add equiv_induct to equiv_assume.ys 2025-08-06 15:13:04 +12:00
Lofty 7537a49f0d
Merge pull request #5241 from Anhijkt/opt_dff-simplify-pt 
opt_dff: implement simplify_patterns
 2025-08-04 09:44:57 +01:00
Rahul Bhagwat 761015b23e
add separate module test 2025-08-03 23:48:33 -04:00
Krystine Sherwin f78cd9d13f
raise_error: Extra test 2025-08-02 14:54:32 +12:00
Krystine Sherwin 895dfd963f
raise_error: Add -always 2025-08-02 14:53:36 +12:00
Robert O'Callahan ffd52a0d8e Making `stringf()` use the format conversion specs as-is without widening them. 
And make sure our fast-path for `%d` and `%u` narrows to `int` correctly.

Resolves #5260
 2025-07-31 10:54:56 +00:00
KrystalDelusion a18acaca82
Merge pull request #5068 from YosysHQ/krys/bugpoint_fixes 
Updates to bugpoint
 2025-07-30 10:05:22 +12:00
Krystine Sherwin fe07d390f1
tests/bugpoint: More tests 
More coverage.
 2025-07-29 11:39:52 +12:00
Krystine Sherwin 93f7429f4f
tests: Add bugpoint to MK_TEST_DIRS 
Also change `-err_grep` to `-err-grep` for consistency with `-expect-return`.
 2025-07-29 11:39:51 +12:00
Krystine Sherwin b5a13ae95b
bugpoint.cc: Rename to -err_grep 2025-07-29 11:39:51 +12:00
Krystine Sherwin fb92eabdcd
bugpoint: Add -greperr option 
`-greperr <string>` redirects stderr to 'bugpoint-case.err', and then searches that file for `<string>`.
Move `-runner` option up with the other options to reduce ambiguity (i.e. so it doesn't look like it's another design parts constraint).
Also some shuffling of `err.ys`.
 2025-07-29 11:39:51 +12:00
Krystine Sherwin 8d5dbae06e
raise_error.cc: Option for direct to stderr 
Add more to help text to describe usage.
Add test for no value (should `exit(1)`).
 2025-07-29 11:39:50 +12:00
Krystine Sherwin 134da811f7
Add raise_error pass 
Raise errors from attributes for testing.
I want it for bugpoint tests but it could be useful elsewhere.
 2025-07-29 11:39:50 +12:00
Robert O'Callahan 8b75c06141 Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
Anhijkt ca8af1f8c8 opt_dff: implement simplify_patterns 2025-07-21 14:15:26 +03:00
KrystalDelusion 5b8b5292ee
Merge pull request #4959 from YosysHQ/krys/primitive_array_error 
simplify: Skip AST_PRIMITIVE in AST_CELLARRAY
 2025-07-21 10:26:00 +12:00
Martin Povišer 9ab1946799
Merge pull request #5209 from povik/hieropt 
Start `opt_hier` to enable hierarchical optimization
 2025-07-17 14:12:18 +02:00
N. Engelhardt d009bcc9b6
Merge pull request #5198 from YosysHQ/nak/lcov 2025-07-17 11:57:58 +02:00
N. Engelhardt fb6974dcd7 print summary of line coverage to log 2025-07-16 13:40:07 +02:00
Krystine Sherwin 5ec189a2f5
Tests: Extra equiv_assume tests 2025-07-16 21:06:04 +12:00
Krystine Sherwin d30f934d0d
equiv_simple: Add -set-assumes option 
Based on existing code for input cone and the `sat` handling of `-set-assumes`.
Update `equiv_assume.ys` to use `-set-assumes` option.
 2025-07-16 21:04:41 +12:00
Krystine Sherwin a57c593c41
tests: Add equiv_assume.ys 2025-07-16 15:32:47 +12:00
Emil J. Tywoniak c7a3abbcc4 libparse: LibertyExpression unit test 2025-07-15 12:53:30 +02:00
Emil J. Tywoniak e960428587 unit tests: fix run failure detection 2025-07-15 12:21:01 +02:00
Emil J. Tywoniak 6ee01308f2 dfflibmap: show dffe inference is broken by space ANDs 2025-07-11 00:33:01 +02:00
Emil J 14aad097f0
Merge pull request #5190 from YosysHQ/emil/dfflibmap-fix-negated-next_state 
dfflibmap: propagate negated next_state to output correctly
 2025-07-10 19:50:02 +02:00
Emil J. Tywoniak 7fe817c52f dfflibmap: test negated state next_state with mixed polarities 2025-07-10 18:54:43 +02:00
N. Engelhardt 02323295b0
Merge pull request #5179 from YosysHQ/krys/assert2cover 2025-07-10 14:53:22 +02:00
Emil J 66035f706e
Merge pull request #5177 from YosysHQ/emil/rename-unescape 
rename: add -unescape
 2025-07-08 10:45:11 +02:00
Martin Povišer 22a44e4333 Start `opt_hier` 2025-07-05 16:45:52 +02:00
Gary Wong 5feb1a1752 verilog: add support for SystemVerilog string literals. 
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
 2025-07-03 20:51:12 -06:00
N. Engelhardt 8a4f465143 update test to use suggested selection for assertions 2025-07-01 11:46:27 +02:00
Krystine Sherwin 017524d7a2
tests/verific: Don't ASAN verific 2025-06-28 11:33:18 +12:00
N. Engelhardt ef3f541501 add linecoverage command to generate lcov report from selection 2025-06-26 13:21:53 +02:00
Emil J. Tywoniak 2b659626a3 rename: add -unescape 2025-06-24 12:33:33 +02:00
Emil J. Tywoniak 73cbcffbbb fixup! dfflibmap: propagate negated next_state to output correctly 2025-06-24 12:31:30 +02:00
Emil J. Tywoniak 778079b058 dfflibmap: propagate negated next_state to output correctly 2025-06-24 12:01:12 +02:00
George Rennie 170933ecb0
Merge pull request #5165 from georgerennie/george/opt_dff_uaf 
opt_dff: don't remove cells until all have been visited to prevent UAF
 2025-06-20 23:33:26 +01:00
garytwong 834a7294b7
verilog: fix string literal regular expression (#5187) 
* verilog: fix string literal regular expression.

A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.

* verilog: add regression test for string literal regex bug.

Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af and fixed by 40aa7eaf).
 2025-06-19 12:41:18 -04:00
Emil J. Tywoniak 4276756f32 fixup! const2ast: add diagnostics tests 2025-06-16 22:50:31 +02:00
Emil J. Tywoniak 49cd3887a7 const2ast: add diagnostics tests 2025-06-16 21:48:12 +02:00
Krystine Sherwin fa68299b25
tests/verific: Add chformal tests 2025-06-14 11:06:38 +12:00
Krystine Sherwin 45131f4425
chformal: Add -assert2cover option 
Also add to chformal tests.
 2025-06-14 10:54:23 +12:00
KrystalDelusion 82888580ac
Merge pull request #5152 from garytwong/unique-if 
verilog: implement SystemVerilog unique/unique0/priority if semantics.
 2025-06-13 09:56:53 +12:00
Emil J c0f52c6ead
Merge pull request #5167 from YosysHQ/emil/fix-splitnets-single-bit-vector 
splitnets: handle single-bit vectors consistently
 2025-06-11 22:47:48 +02:00
George Rennie 7160c91800 tests: add test for #5164 opt_dff -sat UAF 2025-06-06 23:46:23 +01:00
Emil J. Tywoniak 239c265093 splitnets: handle single-bit vectors consistently 2025-06-05 10:58:06 +02:00
George Rennie 0fcf5c080d
Merge pull request #5158 from georgerennie/george/task_inout 
read_verilog/astsimplify: copy inout ports in and out of functions/tasks
 2025-06-04 14:23:08 +01:00
George Rennie ab40403d90
Merge pull request #5154 from georgerennie/george/post_incdec_undo_fix 
read_verilog: fix -1 constant used to correct post increment/decrement
 2025-06-04 14:22:32 +01:00
Emil J c21cd300a0
Merge pull request #5109 from YosysHQ/emil/aiger-map-fix-outputs 
aiger: fix -map and -vmap
 2025-06-02 15:07:19 +02:00
George Rennie 97f51bb4b7 tests: add tests for task/function argument input/output copying 2025-05-31 01:21:06 +01:00
KrystalDelusion 545753cc5a
Merge pull request #5143 from YosysHQ/krys/typedef_struct_global 
SystemVerilog: Fix typedef struct in global space
 2025-05-31 09:59:26 +12:00
George Rennie 3790be114f tests: add tests for verilog pre/post increment/decrement in expressions 2025-05-30 14:38:25 +01:00
Gary Wong 7b09dc31af tests: add cases covering full_case and parallel_case semantics 
This is @KrystalDelusion's suggestion in PR #5141 to verify
sensible implementation of all 4 possible full_case/parallel_case
combinations.

(Also including two similar tests to check the Verilog frontend
applies the correct attributes when given SystemVerilog
priority/unique case and if statements.)
 2025-05-29 20:45:57 -06:00
George Rennie 3ef4c91c31
Merge pull request #5148 from georgerennie/george/convertible_to_int_fix 
Fix convertible_to_int handling of 32 bit unsigned ints with MSB set.
 2025-05-29 10:33:12 +01:00
KrystalDelusion 489a12d6c1
Merge pull request #5141 from garytwong/unique-if 
Accept (and ignore) SystemVerilog unique/priority if.
 2025-05-27 09:45:50 +12:00
George Rennie 353fd0f7f4 tests: test opt_expr for 32 bit unsigned shifts 2025-05-26 15:28:44 +01:00
Krystine Sherwin 995a893afd
Tests: Add svtypes/typedef_struct_global.ys 2025-05-26 12:16:58 +12:00
Gary Wong 73e45d29d6 Add semantic test cases for SystemVerilog priority/unique/unique0 "if". 
The tests/verilog/*_if_enc.ys scripts instantiate simple encoder
modules, both with and without the SystemVerilog priority/unique/unique0
keywords, and check for consistency between the two for the subset
of inputs where the priority/unique/unique0 "if" result is
well-defined.

These tests vacuously succeed at the moment, since priority/unique
keywords are silently ignored and therefore the generated logic is
trivially identical.  But the test cases will be capable of detecting
certain types of unsound optimisation if priority/unique handling is
introduced later.
 2025-05-24 08:44:04 -06:00
Emil J 18abf2d4f7
Merge pull request #5138 from YosysHQ/emil/libcache-verbose 
libcache: add -quiet and -verbose
 2025-05-24 00:05:46 +02:00
Emil J 4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width 
rtlil: enable single-bit vector wires
 2025-05-23 15:55:45 +02:00
Gary Wong 9770ece187 Accept (and ignore) SystemVerilog unique/priority if. 
Add support to the "read_verilog -sv" parser to validate the
"unique", "unique0", and "priority" keywords in contexts where
they're legal according to 1800-2012 12.4.2.

This affects only the grammar accepted; the behaviour of conditionals
is not changed.  (But accepting this syntax will provide scope for
possible optimisations as future work.)

Three test cases ("unique_if", "unique_if_else", and
"unique_if_else_begin") verify that the keywords are accepted where
legal and rejected where illegal, as described in the final paragraph
of 12.4.2.
 2025-05-22 19:28:28 -06:00
George Rennie 6331f92d00
Merge pull request #5101 from georgerennie/george/opt_expr_shift_ovfl 
opt_expr: fix shift optimization with overflowing shift amount
 2025-05-22 15:16:19 +01:00
KrystalDelusion 4c72b0ecd8
Merge pull request #5116 from YosysHQ/krys/update_fst 
Update fstlib
 2025-05-16 09:22:52 +12:00
KrystalDelusion f7888c607b
Merge pull request #5089 from YosysHQ/krys/cutpoint_whole 
cutpoint: Re-add whole module optimization
 2025-05-16 09:22:28 +12:00
Emil J 3823157c25
Merge pull request #5080 from akashlevy/muldiv_c 
Add `muldiv_c` peepopt
 2025-05-15 11:03:25 +02:00
Emil J. Tywoniak e5171d6aa1 verific: support single_bit_vector 2025-05-12 13:23:29 +02:00
Emil J. Tywoniak 5e72464a15 rtlil: enable single-bit vector wires 2025-05-12 13:23:29 +02:00
Krystine Sherwin afd5bbc7fa
fstdata.cc: Fix last step 
Includes test file for sanity checking simulation steps.
 2025-05-12 13:18:19 +12:00
Adrien Prost-Boucle 6bf7587338 URAM mapping : Add test for 2048 x 144b 2025-05-10 14:53:56 +02:00
Emil Jiří Tywoniak cbf069849e aiger: add regression test for sliced output segfault 2025-05-09 16:01:47 +02:00
Emil J. Tywoniak 9d2f9f7557 libcache: fix test 2025-05-09 12:40:38 +02:00
George Rennie d59380b3a0 tests: more complete testing of shift edgecases 2025-05-08 11:09:01 +02:00
George Rennie af933b4f38 tests: check shifts by amounts that overflow int 2025-05-07 15:12:33 +02:00
Krystine Sherwin 7c89355b70
cutpoint: Re-add whole module optimization 
Also add a test script for it.
 2025-05-06 09:57:34 +12:00
Krystine Sherwin 7c2b00c448
tests: Add default param test file 
Just loads, fails ASAN without fix.
 2025-05-05 10:18:52 +12:00
Akash Levy 4bd91fbb11 Add `muldiv_c` peepopt pass 2025-04-30 08:06:59 -07:00
KrystalDelusion bfe05965f9
Merge pull request #5066 from YosysHQ/george/opt_expr_shr_sign 
opt_expr: fix sign extension for shifts
 2025-04-29 09:29:10 +12:00
N. Engelhardt 84c49e1f33
Merge pull request #5041 from jix/declockgate-v2 2025-04-28 13:31:11 +00:00
George Rennie 70a44f035c tests: test opt_expr constant shift edge cases 2025-04-26 12:40:04 +02:00
KrystalDelusion 6564810ae3
Merge pull request #4992 from Anhijkt/fix-ice40dsp-unsigned 
ice40_dsp: fix const handling
 2025-04-26 11:15:02 +12:00
Emil J. Tywoniak 9631f6ece5 liberty: fix tests 2025-04-23 20:20:43 +00:00
Mike Inouye bf8aece4e4 Add test to verify that the liberty format is properly parsed. 2025-04-23 18:40:35 +00:00
Emil J 6a2f2f1818
Merge pull request #5031 from suisseWalter/fix_sequential_area 
stat: fix sequential area not being included in addition/multiplication
 2025-04-21 11:02:40 +02:00
cwalter 41375a5f05 create testcase to check correct addition of areas. 2025-04-20 16:44:22 +02:00
clemens 01d80c7403 add testcase 2025-04-19 20:41:10 +02:00
Jannis Harder 31d6d0ac17 formalff: Fix -declockgate test and missing emit for memories 2025-04-18 18:57:59 +02:00
Jannis Harder bd154a7188 formalff: Add -declockgate option 2025-04-18 17:44:34 +02:00
Jannis Harder 7f7ad87b7b
Merge pull request #5033 from jix/liberty-fixes 
liberty: More robust parsing
 2025-04-17 09:24:42 +02:00
Emil J. Tywoniak c555add231 liberty: Test non-ascii characters 2025-04-17 00:20:18 +02:00
KrystalDelusion 026d161f91
Merge pull request #4923 from KelvinChung2000/const-wrap 
feat: Allow full constant wrapping for hilomap
 2025-04-17 10:16:59 +12:00
Jannis Harder 4b273a4ae9 share: Cleanup and additional testing 
Fixes a typo and adds another test case that triggers the fallback
behavior as the existing tests all trigger the new optimization.
 2025-04-15 12:34:46 +02:00
Kelvin Chung 81f3369f24 Add check at constmap and merge test 2025-04-14 11:44:52 +01:00
Krystine Sherwin 87d3b09988
cutpoint.cc: Fold -instances into -blackbox 
Replace `cutpoint -blackbox` behaviour with `cutpoint -blackbox -instances` behaviour.
Drop `-instances` flag.
Add `-noscopeinfo` flag.
Use `RTLIL::Selection::boxed_module()` helper to shortcut blackbox check.
Update `cutpoint_blackbox.ys` tests to match.
 2025-04-11 04:12:35 +12:00
Krystine Sherwin 779a1fddf6
Testing cutpoint with boxed selections 2025-04-11 04:12:34 +12:00
Krystine Sherwin cf44a9124f
cutpoint: Test -blackbox with parameter 
Modify `cutpoint_blackbox.ys` to check that parameters on blackbox modules are maintained after the cutpoint.
Also adjusts the test to check that each instance gets the `$anyseq` cell.
 2025-04-11 04:12:34 +12:00
Krystine Sherwin 583771ef5b
cutpoint: Add -blackbox option 
Replace the contents of all blackboxes in the design with a formal cut point.
Includes test script.
 2025-04-11 04:12:34 +12:00
N. Engelhardt 3410e10ed5
Merge pull request #5000 from YosysHQ/krys/re_refactor_selections 2025-04-10 16:06:36 +00:00
Kelvin Chung 414dc85573 Correct and more test 2025-04-10 00:01:50 +01:00
Emil J a5e8f52ce5
Merge pull request #4976 from Logikable/main 
Support array ranges for identifiers in the Liberty parser.
 2025-04-09 22:49:52 +02:00
Anhijkt 41a7d4bb81 ice40_dsp: add test 2025-04-09 21:21:46 +03:00
Krystine Sherwin 078602d711
tests/arch/xilinx: Fix for warnings on boxes 
The two test scripts affected use boxed modules directly; under normal usage the warning shouldn't appear.
 2025-04-08 16:58:59 +12:00
Krystine Sherwin 237e454131
design.cc: Fix selections when copying 
Use `Design::selected_modules()` directly, popping at the end instead of copying the selection.
Also default to a complete selection so that boxes work as before.
Simplify to using `RTLIL::SELECT_WHOLE_CMDERR` instead of doing it manually.
Also add tests for importing selections with boxes.
 2025-04-08 16:35:12 +12:00
Krystine Sherwin 911a3ae759
setattr.cc: Use new selection helpers 
Also test they work as expected.
 2025-04-08 15:34:48 +12:00
Krystine Sherwin dbc2611dd6
test_select: Add and exercise test_select pass 
Developer facing, intended to check internal selection semantics work as expected.  i.e. it would have revealed the bug in the now reverted PR.
 2025-04-08 11:59:45 +12:00
Krystine Sherwin f410f98d89
clean ignores boxes 2025-04-08 11:59:40 +12:00
Krystine Sherwin cd3b914132
Reinstate #4768 
Revert the reversion so that we can fix the bugs that the PR missed.
 2025-04-08 11:58:05 +12:00
KrystalDelusion e08aeae1d0
Merge pull request #4989 from YosysHQ/krys/fix_4590 
opt_expr: Fix #4590
 2025-04-08 08:30:18 +12:00
Emil J cc8fd3efc3
Merge pull request #4986 from jix/faster-liberty-caching 
Liberty file caching with new `libcache` command
 2025-04-07 15:15:41 +02:00
Miodrag Milanović d49364d96f
Revert "Refactor full_selection" 2025-04-07 12:11:55 +02:00
KrystalDelusion 98d4355b82
Merge pull request #4768 from YosysHQ/krys/refactor_selections 
Refactor full_selection
 2025-04-05 14:15:27 +13:00
Krystine Sherwin 406b400458
opt_expr: Fix #4590 
If all the (non-select) inputs of a `$_MUX{4,8,16}_` are undefined, replace it, just like we do for `$mux` and `$_MUX_`.
Add `tests/opt/opt_expr_mux_undef.ys` to verify this.

This doesn't do any const folding on the wide muxes, or shrinking to less wide muxes.  It only handles the case where all inputs are 'x and the mux can be completely removed.
 2025-04-04 12:25:31 +13:00
Sean Luchen 307db1ec50 Add tests for #4976. 2025-04-03 10:01:34 -07:00
Sean Luchen bdcbbf2db6 Fix existing tests/liberty tests, and add them to Makefile. 2025-04-03 09:56:24 -07:00
George Rennie 63b3ce0c77
Merge pull request #4971 from Anhijkt/pow-optimization 
opt_expr: optimize pow of 2 cells
 2025-04-03 14:34:36 +02:00
Jannis Harder 0f13b55173 Liberty file caching with new `libcache` command 
This adds optional in-memory caching of parsed liberty files to speed up
flows that repeatedly parse the same liberty files. To avoid increasing
the memory overhead by default, the caching is disabled by default. The
caching can be controlled globally or on a per path basis using the new
`libcache` command, which also allows purging cached data.
 2025-04-03 13:39:35 +02:00
Anhijkt c57cbfa8f9 opt_expr: add test 2025-04-01 21:54:46 +03:00
Emil J 3a1255546a
Merge pull request #4975 from YosysHQ/emil/opt_expr-cover-with-tests 
opt_expr: expand test coverage
 2025-03-31 20:13:16 +02:00
Emil J. Tywoniak 6194eb939d opt_expr: expand test coverage 2025-03-31 19:31:53 +02:00
Emil J 1b25e1cee0
Merge pull request #4942 from Anhijkt/fix-ice40dsp 
ice40_dsp: fix log_assert issue
 2025-03-28 13:32:17 +01:00
Emil J b2816b22c5
Merge pull request #4965 from YosysHQ/krys/gen_err_files 
More *.err files in test failures
 2025-03-28 13:08:44 +01:00
Emil J ec8b745929
Merge pull request #4733 from antmicro/fix-setundef-pass-for-params 
Fix setting bits of parameters in setundef pass
 2025-03-28 13:06:04 +01:00
Kelvin Chung a0dabf9203 Add extra test 2025-03-26 22:24:41 +00:00
KrystalDelusion 5b6b3d01bf
Update gen-tests-makefile.sh 
Keep file extensions so that e.g. tribuf.ys and tribuf.sh don't try to output to the same log file.
 2025-03-27 10:33:51 +13:00
KrystalDelusion 8a68ae6023
Update gen-tests-makefile.sh 2025-03-27 10:10:49 +13:00
Anhijkt cb03a1ec21 ice40_dsp: fix test 2025-03-26 15:13:05 +02:00
Kelvin Chung 7bbdf6049a Move implementation to constmap and add test 2025-03-26 11:52:55 +00:00
Scott Ashcroft 518986d45c Make cxxrtl tests work on 32-bit by using __builtin_clzll when needed 2025-03-25 13:12:04 +00:00
Krystine Sherwin 0a1c664f02
simplify: Skip AST_PRIMITIVE in AST_CELLARRAY 
Otherwise the `AST_PRIMITIVE` simplifies to the corresponding function and is no longer caught by the check for `AST_PRIMITIVE`s, raising an assertion error instead of an input error.
Add bug4785.ys to tests/verilog to demonstrate.
 2025-03-25 12:15:54 +13:00
KrystalDelusion a647731812
Merge pull request #4677 from YosysHQ/emil/opt_merge-hashing 
opt_merge: hashing performance and correctness
 2025-03-25 10:36:02 +13:00
Emil J. Tywoniak 980a0a15c1 stat: allow gzipped liberty files 2025-03-19 13:43:44 +01:00
Anhijkt 5ae32efca5 ice40_dsp: add test 2025-03-15 20:05:57 +02:00
KrystalDelusion 9f1271bee0
Merge pull request #4922 from Anhijkt/fix-splitcells-assert 
splitcells: Fix the assertion bug caused by out-of-bound offset
 2025-03-14 16:52:38 +13:00
Krystine Sherwin 8405b3b723
select: Fix -none and -clear 
If the selection stack only has one element (which it normally does), then
`design->pop_selection()` automatically resets to the default full selection.
This is a problem for `select [-none | -clear]` which were trying to replace the
current selection, but because the pop added an extra element when the `execute`
returned, the extra selection (the one we actually wanted) gets popped too. So
instead, reassign `design->selection()` in the same way as if we called `select
[selection]`.

Also adds selection stack tests, and removes the accidentally-committed
`boxes_dummy.ys`.
 2025-03-14 16:32:18 +13:00
Krystine Sherwin 9a9cd05f6c
tests: Fixes for boxes 
cxxrtl `test_unconnected_output` and simple_abc9 `abc9.v` both expect boxed modules in the outputs, so make sure they work as expected.
 2025-03-14 14:08:15 +13:00
Krystine Sherwin 061c234559
tests/select: Add tests for selections with boxes 2025-03-14 14:05:40 +13:00
Martin Povišer 6da543a61a
Merge pull request #4818 from povik/macc_v2 
Add `$macc_v2`
 2025-03-12 22:55:40 +01:00
Anhijkt be3dfdc5ad splitcells: add tests 2025-03-10 19:41:22 +02:00
Martin Povišer d8a4991289
Merge pull request #4931 from povik/buf-clean 
opt_clean, simplemap: Add `$buf` handling
 2025-03-10 15:10:17 +01:00
Emil J. Tywoniak 33bfc9d19c opt_merge: test more kinds of cells 2025-03-10 13:14:06 +01:00
Emil J. Tywoniak ae7a97cc2d opt_merge: test some unary cells 2025-03-10 13:14:06 +01:00
Emil J. Tywoniak 176faae7c9 opt_merge: fix trivial binary regression 2025-03-10 13:14:06 +01:00
Martin Povišer 557047fe1e opt_clean, simplemap: Add `$buf` handling 2025-03-07 16:08:38 +01:00
N. Engelhardt 268a034b21
Merge pull request #4866 from YosysHQ/ql_ioff 
add IOFF inference for qlf_k6n10f
 2025-03-03 14:12:09 +00:00
Emil J b4a169527d
Merge pull request #4894 from YosysHQ/emil/abstract 
Add `abstract` pass for formal verification
 2025-02-25 11:16:37 +01:00
Emil J. Tywoniak 3f60a2cc67 abstract: test -slice from:to for -init 2025-02-25 00:22:14 +01:00
Emil J. Tywoniak 3cb7054e53 abstract: test -slice for all modes, -rtlilslice for -init 2025-02-25 00:18:16 +01:00
Emil J. Tywoniak 5bd18613bb abstract: test -init 2025-02-19 23:03:43 +01:00
Emil J. Tywoniak 34e3fcbb31 abstract: test -value 2025-02-18 17:08:45 +01:00
Emil J. Tywoniak d3a90021ad abstract: test -state 2025-02-18 17:08:45 +01:00