yosys

Author	SHA1	Message	Date
Robert O'Callahan	8b75c06141	Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.	2025-07-22 10:38:38 +00:00
Catherine	d9a4a42389	write_verilog: don't `assign` to a `reg`. Fixes #2035.	2024-04-03 13:06:45 +02:00
Zachary Snow	207af4196b	fixup verilog doubleslash test - add generated doubleslash.v to .gitignore - ensure backend verilog can be read again	2022-01-03 08:17:46 -07:00
David Shah	c4bfbecca6	Update .gitignore Signed-off-by: David Shah <dave@ds0.me>	2020-10-01 15:53:14 +01:00
Eddie Hung	b11cf67a81	Setup tests/verilog properly	2020-05-11 10:31:02 -07:00