yosys

Author	SHA1	Message	Date
Krystine Sherwin	078602d711	tests/arch/xilinx: Fix for warnings on boxes The two test scripts affected use boxed modules directly; under normal usage the warning shouldn't appear.	2025-04-08 16:58:59 +12:00
Jannis Harder	331ac5285f	tests: Run async2sync before sat and/or sim to handle $check cells Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions.	2024-02-01 16:14:11 +01:00
Eddie Hung	862631d657	Add ABC9 DSP cascade test	2023-05-25 18:42:08 +01:00
Eddie Hung	de79978372	xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325 ) * xilinx: eliminate SCCs from DSP48E1 model * xilinx: add SCC test for DSP48E1 * Update techlibs/xilinx/cells_sim.v * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled	2020-09-23 09:15:24 -07:00