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247 Commits

Author SHA1 Message Date
Marcelina Kościelnicka e6f3d1c225 kernel/mem: Introduce transparency masks. 2021-08-11 00:04:16 +02:00
Marcelina Kościelnicka d25b9088c8 Refactor common parts of SAT-using optimizations into a helper. 
This also aligns the functionality:

- in all cases, the onehot attribute is used to create appropriate
  constraints (previously, opt_dff didn't do it at all, and share
  created one-hot constraints based on $pmux presence alone, which
  is unsound)
- in all cases, shift and mul/div/pow cells are now skipped when
  importing the SAT problem (previously only memory_share did this)
  — this avoids creating clauses for hard cells that are unlikely
  to help with proving the UNSATness needed for optimization
 2021-08-09 16:54:35 +02:00
Marcelina Kościelnicka 63f9e0544f memory_share: Don't skip ports with EN wired to input for SAT sharing. 
Fixes #2912.
 2021-08-04 04:47:43 +02:00
Marcelina Kościelnicka 8733e1923a memory_bram: Move init data swizzling before other swizzling. 
Fixes #2907.
 2021-08-03 15:04:10 +02:00
Marcelina Kościelnicka 4451f7f5e9 memory_bram: Some refactoring 
This will make more sense when the new transparency masks land.

Fixes #2902.
 2021-08-01 16:51:24 +02:00
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 2021-06-08 00:39:36 +02:00
Marcelina Kościelnicka 13b901bf1c memory_map: Improve start_offset handling. 
Fixes #2775.
 2021-05-31 17:45:21 +02:00
Marcelina Kościelnicka 82f5829aba memory_share: Add read port merging. 
This is mostly meant for wide port recognition, but may also happen to
merge some ports with compatible initial/reset values (eg. 0 vs x).
 2021-05-29 16:05:58 +02:00
Marcelina Kościelnicka 2d10caabbc memory_share: Improve sat-based port sharing. 2021-05-28 14:25:33 +02:00
Marcelina Kościelnicka cbf6b719fe Make a few passes auto-call Mem::narrow instead of rejecting wide ports. 
This essentially adds wide port support for free in passes that don't
have a usefully better way of handling wide ports than just breaking
them up to narrow ports, avoiding "please run memory_narrow" annoyance.
 2021-05-28 00:40:56 +02:00
Marcelina Kościelnicka 1eae6025e7 memory_share: Improve same-address merging, recognize wide write ports. 2021-05-27 15:53:12 +02:00
Marcelina Kościelnicka d99fce3bc7 mem/extract_rdff: Fix "no FF made" edge case. 
When converting a sync transparent read port with const address to async
read port, nothing at all needs to be done other than clk_enable change,
and thus we have no FF cell to return.  Handle this case correctly in
the helper and in its users.
 2021-05-25 23:42:31 +02:00
Marcelina Kościelnicka 18806f1ef6 memory_bram: Reuse extract_rdff helper for make_outreg. 
Also properly skip read ports with init value or reset when not making
use of make_outreg.  Proper support for matching those will land later.
 2021-05-25 22:42:03 +02:00
Marcelina Kościelnicka 96c7d60304 memory_bram: Respect write port priority. 2021-05-25 16:28:33 +02:00
Marcelina Kościelnicka e0736c1622 Add memory_narrow pass. 2021-05-25 03:04:13 +02:00
Marcelina Kościelnicka 47f958ce45 memory_share: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka c1a4730739 memory_map: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka 69bf5c81c7 Reject wide ports in some passes that will never support them. 2021-05-25 02:07:25 +02:00
Marcelina Kościelnicka df2b79ca76 memory_share: Use Mem helpers. 2021-05-23 23:16:12 +02:00
Marcelina Kościelnicka afd5366fc2 extract_rdff: Add initvals parameter. 
This is not used yet, but will be needed when read port reset/initial
value support lands.
 2021-05-23 22:05:26 +02:00
Marcelina Kościelnicka d905990d01 memory_share: Split off feedback path finding as a separate pass. 
memory_share is actually three passes in a trenchcoat.  Split off the
one that has the least in common with the other two as a separate pass.
 2021-05-23 18:30:39 +02:00
Marcelina Kościelnicka 1eea06bcc0 Add new helper class for merging FFs into cells, use for memory_dff. 
Fixes #1854.
 2021-05-23 14:46:59 +02:00
Marcelina Kościelnicka 039f4f48d5 memory_memx: Use Mem helper. 2021-05-22 22:31:07 +02:00
Marcelina Kościelnicka 8c734e07b8 memory_dff: Use Mem helper. 2021-05-21 02:26:27 +02:00
Marcelina Kościelnicka a3528649c8 memory_dff: Remove now-useless write port handling. 2021-03-08 20:16:29 +01:00
Marcelina Kościelnicka bc717abad2 memory_dff: Remove code looking for $mux cells. 
This job is now performed by `opt_dff`, which runs before this pass.
 2021-03-08 16:58:12 +01:00
Marcelina Kościelnicka eb76d35e80 memory_dff: Fix needlessly duplicating enable bits. 
When the register being merged into the EN signal happens to be a $sdff,
the current code creates a new $mux for every bit, even if they happen
to be identical (as is usually the case), preventing proper grouping
further down the flow.  Fix this by adding a simple cache.

Fixes #2409.
 2020-10-22 13:03:42 +02:00
Marcelina Kościelnicka 21896e2a02 memory_bram: Use Mem helpers. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka 1e8098279f memory_map: Use Mem helpers. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka d390b380e1 memory_unpack: Use Mem helpers. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka e9978aaf15 memory_collect: Use Mem helpers. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka 248b193d6d memory_nordff: Use Mem helpers. 2020-10-21 17:51:20 +02:00
Marcelina Kościelnicka c9251eb26b memory_dff: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka eae2edf3e4 memory_dff: recognize more dff cells 2020-07-23 20:55:28 +02:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Xiretza edd8ff2c07
Add flooring division operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.

This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
 2020-05-28 22:59:04 +02:00
Xiretza 17163cf43a
Add flooring modulo operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
 2020-05-28 22:59:03 +02:00
David Shah 85672a6c1f memory_bram: Fix ignorance of valid, matched rules 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-10 21:48:04 +01:00
whitequark 93ef516d91
Merge pull request #1603 from whitequark/ice40-ram_style 
ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
 2020-04-10 14:51:01 +00:00
N. Engelhardt 7f33d43e3b
Merge pull request #1890 from boqwxp/cleanup_memory_collect 
Clean up `passes/memory/memory_collect.cc`.
 2020-04-09 14:01:29 +02:00
Alberto Gonzalez 652050b273
Clean up `passes/memory/memory_collect.cc`. 2020-04-09 05:43:05 +00:00
Alberto Gonzalez 685dc37d27
Clean up `passes/memory/memory_unpack.cc`. 2020-04-09 05:38:36 +00:00
whitequark e0def9e4d9 memory_map: add -attr option, to respect inference attributes. 
Before this commit, memory_map (which is always a part of a synth
script) would always pick up any $mem cell that was not processed
by a preceding pass and lower it down to $dff/$mux cells.
This is undesirable for two reasons:
  * If there is an explicit inference attribute set on a $mem cell,
    e.g. (* ram_block *), then it is arguably incorrect to map such
    a memory to $dff/$mux cells.
  * If memory_map tries to lower a memory that was intended to
    be mapped to a large BRAM, it often takes extraordinarily long
    time to finish, produces an extremely large log file, and outputs
    an unusable design.

After this commit, properly invoked memory_map will not map any
memory that has an explicit inference attribute specified, solving
the first issue, and alleviating the second. The default behavior
is not changed.
 2020-04-03 05:51:40 +00:00
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Eddie Hung fdafb74eb7 kernel: use more ID::* 2020-04-02 07:14:08 -07:00
Eddie Hung 37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup 
kernel: speedup by using more pass-by-const-ref
 2020-04-02 07:13:33 -07:00
Eddie Hung 1d93d1e59f memory_share: fix stray brace 2020-03-30 08:35:40 -07:00
Eddie Hung 4d897975a8 Code review fixes 2020-03-30 08:22:46 -07:00
Eddie Hung f64d59d824
Apply suggestions from code review 
Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
 2020-03-30 08:19:56 -07:00
Eddie Hung 7ad7f41bc5 kernel: share a single CellTypes within a pass 2020-03-18 12:21:40 -07:00
Eddie Hung 432a09af80 kernel: SigSpec use more const& + overloads to prevent implicit SigSpec 2020-03-13 08:17:39 -07:00
whitequark 60f047f136 memory_bram: add `attr_icase` option. 
Some vendor toolchains use case insensitive matching for values of
attributes that control BRAM inference.
 2020-02-06 14:58:20 +00:00
Eddie Hung dccd7eb39f Cleanup 2019-12-17 00:25:08 -08:00
Eddie Hung 33e6d05585 Enforce non-existence 2019-12-16 17:06:30 -08:00
Eddie Hung 187e1c46e6 Update doc 2019-12-16 14:48:53 -08:00
Eddie Hung 4158ce4eda More sloppiness, thanks @dh73 for spotting 2019-12-16 13:56:45 -08:00
Eddie Hung 6b384861e4 Oops 2019-12-16 13:31:05 -08:00
Eddie Hung 503d1db551 Implement 'attributes' grammar 2019-12-16 12:58:13 -08:00
Diego H 87e21b0122 Fixing compiler warning/issues. Moving test script to the correct place 2019-12-16 10:23:45 -06:00
Diego H b35559fc33 Merging attribute rules into a single match block; Adding tests 2019-12-15 23:33:09 -06:00
Diego H 266993408a Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific 2019-12-13 15:43:24 -06:00
Clifford Wolf 41e0ddf4f4
Merge pull request #1501 from YosysHQ/dave/mem_copy_attr 
memory_collect: Copy attr from RTLIL::Memory to  cell
 2019-11-27 11:25:23 +01:00
Clifford Wolf 03fb92ed6f Add "opt_mem" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-22 17:45:22 +01:00
David Shah 7ff5d6d30a memory_collect: Copy attr from RTLIL::Memory to cell 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-18 13:58:03 +00:00
Eddie Hung 48d0f99406 stoi -> atoi 2019-08-07 11:09:17 -07:00
Eddie Hung c11ad24fd7 Use std::stoi instead of atoi(<str>.c_str()) 2019-08-06 16:45:48 -07:00
Eddie Hung 046e1a5214 Use State::S{0,1} 2019-08-06 16:22:47 -07:00
Eddie Hung 3486235338 Make liberal use of IdString.in() 2019-08-06 16:18:18 -07:00
Eddie Hung ab3917d079 Error out if enable > dbits 2019-07-13 03:39:23 -07:00
David Shah d45936fe5f memory_dff: Fix checking of feedback mux input when more than one mux 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-02 13:35:50 +01:00
Eddie Hung 42720ef6fe Fix spacing 2019-06-25 08:33:17 -07:00
Eddie Hung c4e4902098 Move only one consumer check outside of while loop 2019-06-25 08:29:55 -07:00
Eddie Hung b7deaceadd Walk through as many muxes as exist for rd_en 2019-06-24 18:33:06 -07:00
David Shah 2bf3ca6443 memory_bram: Fix multiport make_transp 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-07 16:56:31 +01:00
David Shah 6acbc016f4 memory_bram: Consider read enable for address expansion register 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-02 19:47:50 +01:00
David Shah 60594ad40c memory_bram: Reset make_transp when growing read ports 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-27 17:19:14 +00:00
David Shah ac6cc88db3 memory_bram: Fix multiclock make_transp 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-24 16:21:36 +00:00
whitequark 0c318e7db5 memory_collect: do not truncate 'x from \INIT. 
The semantics of an RTLIL constant that has less bits than its
declared bit width is zero padding. Therefore, if the output of
memory_collect will be used for simulation, truncating 'x from
the end of \INIT will produce incorrect simulation results.
 2018-12-21 02:01:27 +00:00
David Shah 2b16d4ed3d memory_dff: Fix typo when checking init value 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-12-18 17:40:01 +00:00
Graham Edgecombe 4fef9689ab memory_bram: Fix initdata bit order after shuffling 
In some cases the memory_bram pass shuffles the order of the bits in a
memory's RD_DATA port. Although the order of the bits in the WR_DATA and
WR_EN ports is changed to match the RD_DATA port, the order of the bits
in the initialization data is not.

This causes reads of initialized memories to return invalid data (until
the initialization data is overwritten).

This commit fixes the bug by shuffling the initdata bits in exactly the
same order as the RD_DATA/WR_DATA/WR_EN bits.
 2018-12-11 21:02:49 +00:00
David Shah 3420ae5ca5 memory_bram: Reset make_outreg when growing read ports 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-19 14:46:31 +01:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Clifford Wolf cee4b1e6bc Disable memory_dff for initialized FFs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-28 17:16:15 +02:00
Clifford Wolf 74efafc1cf Add some cleanup code to memory_nordff 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-28 16:42:06 +02:00
Clifford Wolf 73c01dca65 Add "memory_nordff" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-03-06 23:31:51 +01:00
Kaj Tuomi df4ab169a7 Typo fix. 2016-09-08 10:57:16 +03:00
Clifford Wolf 23afeadb5e Fixed handling of transparent bram rd ports on ROMs 2016-08-27 17:06:22 +02:00
Clifford Wolf cad40fc874 Fixed bug in memory_share for memory ports with different ABITS 2016-08-22 14:26:33 +02:00
Clifford Wolf 15ef608453 Added memory_memx pass, "memory -memx", and "prep -memx" 2016-08-19 19:48:26 +02:00
Clifford Wolf f6629b9c29 Optimize memory address port width in wreduce and memory_collect, not verilog front-end 2016-08-19 18:38:25 +02:00
Clifford Wolf ffcdc53a18 Don't sign-extend memory bram initialization data 2016-05-15 00:05:30 +02:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf 1761d08dd2 Bugfix and improvements in memory_share 2016-04-21 14:22:58 +02:00
Clifford Wolf ec93680bd5 Renamed opt_share to opt_merge 2016-03-31 08:52:49 +02:00
Clifford Wolf bcc873b805 Fixed some visual studio warnings 2016-02-13 17:31:24 +01:00
Clifford Wolf ddf3e2dc65 Bugfix in memory_dff 2015-10-31 22:01:41 +01:00
Clifford Wolf 207736b4ee Import more std:: stuff into Yosys namespace 2015-10-25 19:30:49 +01:00
Clifford Wolf 4864736167 Bugfix in bram read-enable code 2015-09-25 14:22:33 +02:00
Clifford Wolf 924d9d6e86 Added read-enable to memory model 2015-09-25 12:23:11 +02:00
Clifford Wolf 3501f8e364 Fixed memory_bram for ROMs in BRAMs with write-enable inputs 2015-09-24 11:37:15 +02:00