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2021 Commits

Author SHA1 Message Date
KrystalDelusion 82888580ac
Merge pull request #5152 from garytwong/unique-if 
verilog: implement SystemVerilog unique/unique0/priority if semantics.
 2025-06-13 09:56:53 +12:00
N. Engelhardt f22248f056 downgrade verific warnings about common coding styles 2025-06-06 16:30:50 +02:00
Emil J 378add3723
Merge pull request #5163 from YosysHQ/emil/fix-single-bit-vector-leak 
simplify: fix single_bit_vector memory leak
 2025-06-04 17:00:54 +02:00
George Rennie 0fcf5c080d
Merge pull request #5158 from georgerennie/george/task_inout 
read_verilog/astsimplify: copy inout ports in and out of functions/tasks
 2025-06-04 14:23:08 +01:00
George Rennie ab40403d90
Merge pull request #5154 from georgerennie/george/post_incdec_undo_fix 
read_verilog: fix -1 constant used to correct post increment/decrement
 2025-06-04 14:22:32 +01:00
Emil J. Tywoniak c37b7b3bf4 simplify: fix single_bit_vector memory leak 2025-06-04 10:32:03 +02:00
Gary Wong ca7d94af99 verilog: improve string literal matching speed (fixes #5076) 
Use a greedy regular expression to match input inside a string
literal, so that flex can accumulate a longer match instead of
invoking a rule for each individual character.
 2025-05-31 22:38:44 -06:00
George Rennie 45e8ff476e read_verilog: copy inout ports in and out of functions/tasks 2025-05-31 01:09:03 +01:00
KrystalDelusion 545753cc5a
Merge pull request #5143 from YosysHQ/krys/typedef_struct_global 
SystemVerilog: Fix typedef struct in global space
 2025-05-31 09:59:26 +12:00
George Rennie 70291f0e49 read_verilog: fix -1 constant used to correct post increment/decrement 2025-05-30 14:38:25 +01:00
Gary Wong 370d5871f4 verilog: implement SystemVerilog unique/unique0/priority if semantics. 
There are two elements involved:

1) Apply the relevant full_case and/or parallel_case attribute(s) to
the generated AST_CASE node(s), so that the existing AST frontend and
subsequent passes will generate RTLIL with appropriate behaviour.
(This is handled in the parser "if_attr" non-terminal.)

2) Rearrange the AST_CASE structure when necessary.  For "priority if"
(i.e., full_case), this requires only ensuring that directly nested
"else if" branches also inherit the full_case attribute.  For
"unique if" and "unique0 if" (i.e., parallel_case+full_case and
parallel_case alone), there are two steps:
    a) Flatten the AST_CASE structure such that any direct "else if"
    branches are mapped to additional AST_CONDs in the parent;
    b) Reverse the "direction" of the test: the constant 1 (true)
    is provided in the AST_CASE node, and the expression(s) in the
    if statement(s) are given in each AST_COND.  This is necessary
    because the constant 1, being the common factor, must occupy the
    shared AST_CASE position.
(This is handled in the parser "TOK_IF" expansion of behavioral_stmt.)

Observe that:
 * The generated AST has not been changed for bare "if"s (those
 without unique/priority).  This should minimise the risk of
 unexpected regressions.

 * It is possible that the flattening described in 2) a) above might
 affect the behaviour of expressions with side effects in "unique if"
 statements (consider "unique if( a ) ...; else if( b++ ) ...": if
 a is true, is b incremented?).  While it might be possible to provide
 precise semantics here, IEEE 1800-2012 12.4.2 seems to be deliberately
 vague ("In unique-if and unique0-if, the conditions may be evaluated
 and compared in any order[...] The presence of side effects in
 conditions may cause nondeterministic results.") and so it seems
 doubtful that there is benefit in Yosys providing stronger promises
 on the interpretation of questionable code.
 2025-05-29 20:45:57 -06:00
KrystalDelusion 489a12d6c1
Merge pull request #5141 from garytwong/unique-if 
Accept (and ignore) SystemVerilog unique/priority if.
 2025-05-27 09:45:50 +12:00
Krystine Sherwin 32ce23458f
read_verilog: Mark struct as custom type 
Being a custom type means that it will be resolved *before* (e.g.) a wire can use it as a type.
 2025-05-26 12:19:33 +12:00
Emil J 4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width 
rtlil: enable single-bit vector wires
 2025-05-23 15:55:45 +02:00
Gary Wong 9770ece187 Accept (and ignore) SystemVerilog unique/priority if. 
Add support to the "read_verilog -sv" parser to validate the
"unique", "unique0", and "priority" keywords in contexts where
they're legal according to 1800-2012 12.4.2.

This affects only the grammar accepted; the behaviour of conditionals
is not changed.  (But accepting this syntax will provide scope for
possible optimisations as future work.)

Three test cases ("unique_if", "unique_if_else", and
"unique_if_else_begin") verify that the keywords are accepted where
legal and rejected where illegal, as described in the final paragraph
of 12.4.2.
 2025-05-22 19:28:28 -06:00
Emil J. Tywoniak e5171d6aa1 verific: support single_bit_vector 2025-05-12 13:23:29 +02:00
Emil J. Tywoniak 5e72464a15 rtlil: enable single-bit vector wires 2025-05-12 13:23:29 +02:00
Krystine Sherwin fe0abb7026
simplify.cc: Fix mem leak 2025-05-10 17:10:47 +12:00
KrystalDelusion 547382504b
Update verilog_frontend.cc 
`read_verilog_file_list` should not try to read arguments as selection args.  Without this, trying to pass a file without a `-f|-F` flag is misleading, in the best case giving a warning about the selection not matching any module, or in worst case just doing nothing (if the filename is a valid selection).
 2025-05-08 10:37:04 +12:00
Krystine Sherwin 23cb007068
verilog_parser.y: Delete unused TOK_ID 
Fixes memory leak when parameter has no value.
 2025-05-05 10:04:13 +12:00
N. Engelhardt 8bdbf797d0
Merge pull request #5017 from YosysHQ/micko/ram_blasting 2025-04-28 13:33:48 +00:00
Emil J. Tywoniak bdc2597f79 simplify: fix struct wiretype attr memory leak 2025-04-25 01:00:08 +02:00
Miodrag Milanovic 22e6ce4282 verific: bit blast RAM if using mem2reg attribute 2025-04-14 15:24:11 +02:00
Miodrag Milanovic 406ee4c8d3 read_verilog_file_list: change short help message to start with lower case 2025-04-08 13:20:16 +02:00
Jannis Harder 0f13b55173 Liberty file caching with new `libcache` command 
This adds optional in-memory caching of parsed liberty files to speed up
flows that repeatedly parse the same liberty files. To avoid increasing
the memory overhead by default, the caching is disabled by default. The
caching can be controlled globally or on a per path basis using the new
`libcache` command, which also allows purging cached data.
 2025-04-03 13:39:35 +02:00
Miodrag Milanovic 72f2185a94 verific: fix restoring msg state after blackbox import 2025-04-01 17:35:59 +02:00
Krystine Sherwin 0a1c664f02
simplify: Skip AST_PRIMITIVE in AST_CELLARRAY 
Otherwise the `AST_PRIMITIVE` simplifies to the corresponding function and is no longer caught by the check for `AST_PRIMITIVE`s, raising an assertion error instead of an input error.
Add bug4785.ys to tests/verilog to demonstrate.
 2025-03-25 12:15:54 +13:00
Emil J. Tywoniak 813f909460 gzip: istream 2025-03-19 13:43:44 +01:00
Emil J. Tywoniak 4f3fdc8457 io: refactor string and file work into new unit 2025-03-19 13:43:42 +01:00
Jason Xu a5f34d04f8 Address comments 2025-03-11 18:50:44 -04:00
Jason Xu 98eefc5d1a Add file list support to read pass 2025-03-07 20:44:21 -05:00
Jason Xu bf1eab565b Fix compile on WASI platform 2025-03-07 20:20:27 -05:00
Jason Xu ac31bad656 Address all comments 2025-03-07 20:16:28 -05:00
Jason Xu 8ec96ec806 Address most comments 2025-03-07 20:16:28 -05:00
Jason Xu 0678c4dec9 Coding style update 2025-03-07 20:16:28 -05:00
Jason Xu f62a9be153 Initial file list support 2025-03-07 20:16:28 -05:00
Emil J 39aacc95df
Merge pull request #4907 from YosysHQ/emil/fix-clear-preset-latch 
liberty: fix clear and preset latches
 2025-03-03 18:53:12 +01:00
Martin Povišer 732ed67014 ast/dpicall: Stop using variable length array 
Fix the compiler warning

    variable length arrays in C++ are a Clang extension [-Wvla-cxx-extension]
 2025-02-24 17:32:30 +01:00
Emil J. Tywoniak 2b33937ab8 liberty: fix clear and preset latches 2025-02-17 17:36:51 +01:00
KrystalDelusion cf52cf3009
nowrshmsk: Check for stride==0 
log2(0) returns -inf, which gives undefined behaviour when casting to an int.  So catch the case when it's 0 just set the width to 0.
 2025-01-31 12:15:53 +13:00
N. Engelhardt d640157ec4 fix some cases of hdlname being added to objects with private names 2025-01-15 15:56:42 +01:00
Emil J. Tywoniak a58481e9b7 mark all hash_into methods nodiscard 2025-01-14 12:39:15 +01:00
Emil J. Tywoniak b9b9515bb0 hashlib: hash_eat -> hash_into 2024-12-18 15:09:25 +01:00
Emil J. Tywoniak 4e29ec1854 hashlib: acc -> eat 2024-12-18 15:09:25 +01:00
Emil J. Tywoniak d071489ab1 hashlib: redo interface for flexibility 2024-12-18 14:49:25 +01:00
N. Engelhardt 378864d33b bound attributes: handle vhdl null ranges 2024-12-12 11:42:39 +01:00
N. Engelhardt 03033ab6d4 add more tests for bounds attributes, fix attributes appearing in verilog 2024-12-11 16:11:02 +01:00
Martin Povišer ea38fcca5e
Merge pull request #4737 from povik/abc_new-design-boxes 
Support `abc9_box` on ordinary modules in abc_new
 2024-12-10 20:07:56 +01:00
Martin Povišer e9c7967d1e
Merge pull request #4804 from povik/read_liberty-comb-cells 
read_liberty: Revisit for abc9 whiteboxes
 2024-12-10 17:50:21 +01:00
Martin Povišer 6b343c2600 aiger2: Clean debug print 2024-12-10 14:27:55 +01:00
Martin Povišer a353b8fff0 read_liberty: Directly set `abc9_box` on fitting cells 2024-12-09 15:43:41 +01:00
Miodrag Milanovic 7d4aff618f verific: Disable module existence check during static elaboration 2024-12-06 15:59:09 +01:00
Martin Povišer cf0a583f40 read_xaiger2: Rm debug print 2024-12-05 18:33:20 +01:00
Martin Povišer 5dffdd229c read_liberty: Redo unit delay; add `simple_comb_cell` attr 2024-12-05 18:31:24 +01:00
KrystalDelusion c96d02b204
Merge pull request #4784 from YosysHQ/krys/reduce_warnings 
Reduce number of warnings
 2024-12-05 09:16:06 +13:00
Krystine Sherwin e634e9c26b
aiger2: Resolve warnings 
- Remove unused statics CONST_FALSE and CONST_TRUE (which appear to have been folded into the `Index` declaration as CFALSE and CTRUE).
- Assign default value of EMPTY_LIT to `a` and `b` for comparison ops.
- Tag debug only variables with YS_MAYBE_UNUSED, don't assign unused variables (but continue to call the function because it moves the file pointer).
 2024-12-03 14:01:57 +13:00
Miodrag Milanovic 912b38eedb verific: Handle crash when using empty box option 2024-12-02 15:45:12 +01:00
Krystine Sherwin 1de5d98ae2
Reduce comparisons of size_t and int 
`Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`.
For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
 2024-11-29 12:53:29 +13:00
Martin Povišer 3bab837bc9
Merge pull request #4765 from georgerennie/george/rtlil_case_rule 
read_rtlil: Warn on assigns after switches in case rules
 2024-11-28 00:01:21 +01:00
Miodrag Milanović 29e8812bab
Merge pull request #4724 from YosysHQ/micko/blackbox_verific 
verific: fix blackbox regression and add test case
 2024-11-25 15:06:54 +01:00
George Rennie 4a057b3c44 read_rtlil: warn on assigns after switches in case rules 2024-11-21 22:41:13 +01:00
Miodrag Milanovic d6bd521487 verific : VHDL assert DFF initial value set on Verific library patch side 2024-11-21 13:43:26 +01:00
Martin Povišer 1cb5fd08b7
Merge pull request #4682 from povik/read_liberty-extensions 
read_liberty extensions
 2024-11-18 14:42:18 +01:00
Mike Inouye 06e3ac4415 Fix bug when setting Verific runtime string flags. 
Signed-off-by: Mike Inouye <mikeinouye@google.com>
 2024-11-12 18:46:26 +00:00
Martin Povišer 0d5c412807 read_liberty: s/busses/buses/ 2024-11-12 13:33:41 +01:00
Martin Povišer 28aa7b00ee read_liberty: Start an `-ignore_busses` option 2024-11-12 13:26:38 +01:00
Martin Povišer 0e96e477a2 read_liberty: Defer handling of re-definitions 
Postpone handling re-definitions to after we have established the cell
is not supposed to be ignored on the grounds of one of the user-provided
flags.
 2024-11-12 13:26:38 +01:00
Martin Povišer c7e8d41600 read_liberty: Set `area` `capacitance` attributes 2024-11-12 13:26:38 +01:00
Miodrag Milanovic df391f5816 verific: fix blackbox regression and add test case 2024-11-08 14:57:04 +01:00
Krystine Sherwin ee73a91f44
Remove references to ilang 2024-11-05 12:36:31 +13:00
George Rennie dbfca1bdff frontends/ast.cc: special-case zero width strings as "\0" 
* Fixes #4696
 2024-11-01 17:19:28 +01:00
Emil J. Tywoniak 81bbde62ca verilog_parser: silence yynerrs warning 2024-10-15 08:32:55 -04:00
Emil J caf56ca3e8
Merge pull request #4516 from YosysHQ/emil/src-attribute-std-string-wip 
Represent string constants as strings
 2024-10-14 06:42:54 -07:00
Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Miodrag Milanovic 8d2b63bb8a Set VHDL assert condition initial state if fed by FF 2024-10-11 16:32:21 +02:00
Martin Povišer 0aab8b4158
Merge pull request #4605 from povik/liberty-unit-delay 
read_liberty: Optionally import unit delay arcs
 2024-10-07 16:11:51 +02:00
Martin Povišer 74e92d10e8
Merge pull request #4593 from povik/aiger2 
New aiger backend
 2024-10-07 16:11:25 +02:00
Martin Povišer 7989d53c58 read_xaiger2: Add help 2024-10-07 14:19:49 +02:00
Martin Povišer f44a418212 read_xaiger2: Add casts to silence warnings 2024-10-07 12:27:54 +02:00
Martin Povišer 8d12492610 read_xaiger2: Fix detecting the end of extensions 2024-10-07 12:03:48 +02:00
Martin Povišer 2b1b5652f1 Adjust `read_xaiger2` prints 2024-10-07 12:03:48 +02:00
rherveille ce7db661a8
Added cast to type support (#4284) 2024-09-29 17:03:01 -04:00
Martin Povišer f168b2f4b1 read_xaiger2: Update box handling 2024-09-18 16:55:02 +02:00
Martin Povišer 1ab7f29933 Start read_xaiger2 -sc_mapping 2024-09-18 16:42:56 +02:00
Martin Povišer 4976abb867 read_liberty: Optionally import unit delay arcs 2024-09-18 16:17:03 +02:00
N. Engelhardt c8b42b7d48
Merge pull request #4538 from RCoeurjoly/verific_bounds 2024-09-12 13:04:04 +02:00
Emil J. Tywoniak 1372c47036 internal_stats: astnode (sizeof) 2024-09-11 11:34:20 +02:00
Roland Coeurjoly bdc43c6592 Add left and right bound properties to wire. Add test. Fix printing 
for signed attributes

Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-09-10 12:52:42 +02:00
Roland Coeurjoly 27c1432253 Remove log 2024-08-21 14:28:42 +01:00
Roland Coeurjoly 91e3773b51 Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting 2024-08-21 14:28:42 +01:00
Martin Povišer ab5d6b06b4 read_liberty: Fix omitted helper change 2024-08-13 20:12:38 +02:00
Martin Povišer 309d80885b read_liberty: Use available gate creation helpers 2024-08-13 18:47:36 +02:00
Martin Povišer 3057c13a66 Improve libparse encapsulation 2024-08-13 18:47:36 +02:00
Miodrag Milanović 3e14e67374
Merge pull request #4500 from YosysHQ/micko/vhdl_mixcase 
VHDL is case insensitive, make sure netlist name is proper
 2024-07-29 16:44:13 +02:00
Miodrag Milanovic 405897a971 Update top value that is returned back to hierarchy pass 2024-07-29 15:50:38 +02:00
Miodrag Milanovic 9566709426 Initialize extensions when verific pass is registered 2024-07-25 11:25:17 +02:00
Miodrag Milanovic c94aa719d9 VHDL is case insensitive, make sure netlist name is proper 2024-07-18 16:56:52 +02:00
Emil J. Tywoniak 72a0380da8 ast: don't suggest use in external projects 2024-07-18 16:37:14 +02:00
gatecat 22d8df1e7e liberty: Support for IO liberty files for verification 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-06-19 21:12:42 +02:00
Miodrag Milanovic dfde792288 Refactored import code 2024-06-17 14:49:58 +02:00
Miodrag Milanovic 19da7f7d59 Update makefile to make options uniform 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 0f3f731254 Handle -work for vhdl, and clean messages 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 0a81c8e161 Import all modules from all libraries when when needed 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 7c3094633d Compile with hier_tree separate SV and VHDL as well 2024-06-17 13:29:11 +02:00
Miodrag Milanovic e2e189647f Cleanup 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 7bec332b68 SV + VHDL with RTL support 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 25d50bb2af VHDL only build support 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 54bf9ccf06 Add initial support for Verific without additional YosysHQ patch 2024-06-17 13:29:11 +02:00
Martin Povišer b593f5c01c Update the overview comment in `ast.h` 2024-06-10 16:38:39 +02:00
Mike Inouye b0ab1cf8c3 Fix memory leak in verific file parsing. 
Signed-off-by: Mike Inouye <mikeinouye@google.com>
 2024-06-07 22:51:28 +00:00
Miodrag Milanović 1a54e8d47b
Merge pull request #4379 from QuantamHD/fix_verific 
frontend: Fixes verific import around range order
 2024-05-09 11:52:34 +02:00
Ethan Mahintorabi 82a4a87c97
Fixes error with vector indicies of the form [2:7] [-12:7] 
Make sure that we correctly adjust the value to align it to a zero
indexed list with lsb = 0

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-08 20:29:47 +00:00
Ethan Mahintorabi c039da2ec1
renames variables for more code clairty 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-08 01:09:52 +00:00
Ethan Mahintorabi a2c1b268d9
frontend: Fixes verific import around range order 
Test Case
```
module packed_dimensions_range_ordering (
    input  wire [0:4-1] in,
    output wire [4-1:0] out
);
  assign out = in;
endmodule : packed_dimensions_range_ordering

module instanciates_packed_dimensions_range_ordering (
    input  wire [4-1:0] in,
    output wire [4-1:0] out
);
  packed_dimensions_range_ordering U0 (
      .in (in),
      .out(out)
  );
endmodule : instanciates_packed_dimensions_range_ordering
```

```
// with verific, does not pass formal
module instanciates_packed_dimensions_range_ordering(in, out);
  input [3:0] in;
  wire [3:0] in;
  output [3:0] out;
  wire [3:0] out;

  assign out = { in[0], in[1], in[2], in[3] };
endmodule

// with surelog, passes formal
module instanciates_packed_dimensions_range_ordering(in, out);
  input [3:0] in;
  wire [3:0] in;
  output [3:0] out;
  wire [3:0] out;

  assign out = in;
endmodule
```

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-08 01:00:06 +00:00
Krystine Sherwin df95ea824b read_verilog: Add missing defaults for flags 
Fix for YosysHQ/sby#103
 2024-05-07 20:25:36 +02:00
George Rennie 4e6deb53b6 read_aiger: Fix incorrect read of binary Aiger without outputs 
* Also makes all ascii parsing finish reading lines and adds a small
  test
 2024-04-29 14:06:58 +01:00
KrystalDelusion c3ae33da33
Merge pull request #4285 from YosysHQ/typo_fixup 
Typo fixing
 2024-04-25 09:54:48 +12:00
Miodrag Milanovic af94123730 verific: expose library name as module attribute 2024-04-15 17:01:07 +02:00
N. Engelhardt 3d5e23e585
Merge pull request #4302 from YosysHQ/vhdl_2019 
Verific support for VHDL 2019
 2024-04-09 18:25:05 +02:00
N. Engelhardt 18afa36acd
Merge pull request #4273 from YosysHQ/vhdl_params 
verific: Improve import VHDL constants
 2024-04-09 18:01:41 +02:00
Catherine a5441bc00c fmt: `FmtPart::{STRING→LITERAL},{CHARACTER→STRING}`. 
Before this commit, the `STRING` variant inserted a literal string;
the `CHARACTER` variant inserted a string. This commit renames them
to `LITERAL` and `STRING` respectively.
 2024-04-02 12:13:22 +02:00
Miodrag Milanovic f536de0e0e Verific support for VHDL 2019 2024-03-28 13:21:55 +01:00
Miodrag Milanovic 4367e176fb code split and cleanup 2024-03-19 09:15:04 +01:00
Miodrag Milanovic 9eebc80170 handle standard types 2024-03-18 10:35:01 +01:00
Krystine Sherwin 3eeefd23e3
Typo fixup(s) 2024-03-18 11:09:23 +13:00
Miodrag Milanovic 7c09fa572e real number handling and default to string 2024-03-14 10:37:56 +01:00
Miodrag Milanovic 4279cea33a improve handling VHDL constants 2024-03-14 10:37:56 +01:00
Miodrag Milanovic 858eae5572 verific_const: convert VHDL values to RTLIL consts 2024-03-14 10:37:56 +01:00
Martin Povišer b16f4900fd ast/simplify: Interpret hdlname w/o expecting backslash 2024-02-13 21:38:41 +01:00
Catherine d8ce26a5ba read_verilog: correctly format `hdlname` attribute value. 
The leading slash is not a part of the attribute as it only concerns
public values.
 2024-02-13 18:41:53 +00:00
Miodrag Milanovic ae7daf99f4 Verific: Add attributes to module instantiation 2024-02-12 09:53:47 +01:00
Dag Lem f09ea16bd1 Resolve struct member multiple dimensions defined in stages with typedef 2024-02-11 11:26:52 -05:00
Dag Lem 03f35c3def Resolve multiple dimensions defined in stages with typedef 2024-02-11 11:26:52 -05:00
Dag Lem e0d3977e19 Add support for $dimensions and $unpacked_dimensions 2024-02-11 11:26:52 -05:00
Dag Lem 2125357e76 Add support for $increment 2024-02-11 11:26:52 -05:00
Dag Lem 88d9e213cb Decoding of a few more AST nodes in dumpVlog 2024-02-11 11:26:52 -05:00
Dag Lem 39fea32c6e Add support for packed multidimensional arrays 
* Generalization of dimensions metadata (also simplifies $size et al.)
* Parsing and elaboration of multidimensional packed ranges
 2024-02-11 11:26:52 -05:00
Catherine 1236bb65b6 read_verilog: don't include empty `opt_sva_label` in span. 
Consider this SystemVerilog file:

    module top(...);
      input clk;
      input [7:0] data;
      input ack;

      always @(posedge clk)
        if (ack) begin
          assert(data != 8'h0a);
        end
    endmodule

Before this commit, the span for the assert was:

        if (ack) begin>
          assert(data != 8'h0a)<;

After this commit, the span for the assert is:

        if (ack) begin
          >assert(data != 8'h0a)<;

This helps editor integrations that only look at the beginning
of the span.
 2024-02-08 14:25:35 +00:00
Miodrag Milanović 5d3e4c5c7a
Merge pull request #4182 from QuantamHD/fix_aldff 
verific: Improves aldff inference in verific importer
 2024-02-06 08:19:43 +01:00
N. Engelhardt 2422dd6845
Merge pull request #4153 from Coloquinte/blif_delay_constraints 
Issue a warning instead of a syntax error for blif delay constraints
 2024-02-05 15:14:05 +01:00
Ethan Mahintorabi ff578ecabd
fix formatting 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-02-05 07:23:04 +00:00
Ethan Mahintorabi bc66dfd9ea
verific: Fixes incorrect aldff inference in verific importer 
The following SV module at HEAD imported with verific,

```systemverilog
    module my_module(
      input logic [4:0] a,
      input logic clk,
      input logic enable,
      output logic [4:0] z
    );

    reg [4:0] pipeline_register;
    always @(posedge clk) begin
      pipeline_register <= enable ? a : pipeline_register;
    end
    assign z = pipeline_register;

    endmodule : my_module

```

results in the following output verilog

```systemverilog
/* Generated by 0.36 */

(* top =  1  *)
(* hdlname = "my_module" *)
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:2.12-2.21" *)
module my_module(clk, enable, a, z);
  wire [4:0] _0_;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:3.25-3.26" *)
  input [4:0] a;
  wire [4:0] a;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:4.19-4.22" *)
  input clk;
  wire clk;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:5.19-5.25" *)
  input enable;
  wire enable;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:6.26-6.27" *)
  output [4:0] z;
  wire [4:0] z;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:10.12-12.8" *)
  \$aldff  #(
    .ALOAD_POLARITY(32'd1),
    .CLK_POLARITY(32'd1),
    .WIDTH(32'd5)
  ) _1_ (
    .AD(5'hxx),
    .ALOAD(1'h0),
    .CLK(clk),
    .D(_0_),
    .Q(z)
  );
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:11.28-11.58" *)
  \$mux  #(
    .WIDTH(32'd5)
  ) _2_ (
    .A(z),
    .B(a),
    .S(enable),
    .Y(_0_)
  );
endmodule
```

Yosys is incorrectly infering aldffs due to an incorrect conversion
of logical 1 and 0 SigBits.

My PR unifies the conversion of Verific::Net objects into SigBits using
Yosys' internal representation of special signals like 0,1,x,z. After
my PR these signals are correctly converted into DFFs.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-02-05 07:10:25 +00:00
Catherine c7bf0e3b8f Add new `$check` cell to represent assertions with a message. 2024-02-01 20:10:39 +01:00
Miodrag Milanovic db1de5fe5d verific: add option to skip simplifying complex ports 2024-01-30 16:33:44 +01:00
Gabriel Gouvine c634d59c18 Issue a warning instead of a syntax error for blif delay constraints 2024-01-23 16:25:16 +00:00
Miodrag Milanovic 1764c0ee3c Fix verific clocking when no driver exist 2024-01-18 08:47:04 +01:00
Martin Povišer 149bcd88ad
Merge pull request #4026 from uis246/fix-format 
Fix printf formats
 2024-01-15 16:04:11 +01:00
uis 5902b2826d Fix printf formats 2024-01-15 12:07:54 +01:00
Catherine 1159e48721 write_verilog: emit `initial $display` correctly. 2024-01-11 13:13:04 +01:00
Dag Lem 3ed9030eb4 Optionally suppress output from display system tasks in read_verilog 2024-01-11 13:12:53 +01:00