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2530 Commits

Author SHA1 Message Date
Lofty 1ceb5b2930 analogdevices: double LUT RAM cost 2025-11-09 15:44:35 +00:00
Lofty 22e04ac81e analogdevices: ignore $assert cells 2025-11-09 15:44:35 +00:00
Krystine Sherwin fc2e468fd9 analogdevices: Fixing up bram 
Tested all the accepted configurations in eXpreso, disabling the RBRAM2 configs that fail to place, and increasing the cost for the double site TDP memories.
 2025-11-09 15:44:35 +00:00
Krystine Sherwin 2ab84648b4 analogdevices: Add BRAM options 
Enable `-force-params`, and tidy up lutram mapping too.
 2025-11-09 15:44:35 +00:00
Lofty f8fc7bfd3d analogdevices: LUT RAM only on positive edge 2025-11-09 15:44:35 +00:00
Lofty 8101eca236 analogdevices: DSP tweaks 2025-11-09 15:44:35 +00:00
Lofty 0261d18759 analogdevices: DSP inference 2025-11-09 15:44:35 +00:00
Lofty d62d789ce4 analogdevices: remove cells_xtra 2025-11-09 15:44:35 +00:00
Lofty dd5fbebe8e analogdevices: timings for t40lp 2025-11-09 15:44:35 +00:00
Lofty 47c5a52674 analogdevices: use single tech param 2025-11-09 15:44:35 +00:00
Lofty 4aa5008c56 analogdevices: expreso does not care about clock buffers 2025-11-09 15:44:35 +00:00
Lofty 3e1ca2f3e6 analogdevices: prepare for t40lp timings 2025-11-09 15:44:35 +00:00
Krystine Sherwin dc76af06a0 analogdevices: Adding RBRAM2 and -tech 2025-11-09 15:44:34 +00:00
Krystine Sherwin 3f90865a28 analogdevices: (some) Native BRAM 
Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
 2025-11-09 15:44:34 +00:00
Krystine Sherwin d5074c5849 analogdevices: Native LUTRAM primitives 2025-11-09 15:44:34 +00:00
Lofty a2983851f0 analogdevices: LUTRAM config 2025-11-09 15:44:34 +00:00
Lofty 2b384b8d53 analogdevices: update timing model 2025-11-09 15:44:34 +00:00
Lofty af57ebafa0 analogdevices: user retargeting 2025-11-09 15:44:34 +00:00
Lofty a5271bc482 analogdevices: more housekeeping 2025-11-09 15:44:34 +00:00
Lofty 5abb8fd6f1 analogdevices: remove some extra cells! 2025-11-09 15:44:34 +00:00
Lofty 9f26034176 test suite 2025-11-09 15:44:34 +00:00
Lofty a1d13843ad synth_analogdevices: remove scopeinfo cells 2025-11-09 15:44:34 +00:00
Lofty f4c003b1c5 Create synth_analogdevices 2025-11-09 15:44:34 +00:00
KrystalDelusion 39fab4a07f
Makefile: Add gatemate genfiles 
Allows files to be cleaned with `make clean`, without which it breaks out-of-tree builds if an in-tree build has previously run and subsequently cleaned.
 2025-11-04 11:46:27 +13:00
YRabbit 2a3720921c Gowin. Fix GW5A ADCs. 
For these primitives, Gowin decided to use a different option for
describing ports—directly in the module header, i.e.

``` verilog
module ADC(input CLK);
```

instead of
``` verilog
module ADC(CLK);
input CLK;
```

Since this one-time parser becomes too confusing, it is easier to simply
add ADC descriptions as they are from a separate file, especially since
these primitives are only available in the GW5A series.

Test:
``` shell
yosys -p "read_verilog top.v; synth_gowin -json top-synth.json -family gw5a"
```

The old version of Yosys simply won't compile the design due to the lack
of port descriptions, while the new version will compile without errors.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-10-29 12:48:21 +10:00
Patrick Urban 14c1802b01 gatemate: fix SERDES CDR parameters 2025-10-27 15:47:48 +01:00
YRabbit 3956f103a9 Gowin. Handle the WRITE_MODE. 
Process the WRITE_MODE in the GW5A series in a more concise manner.

You can check it in the same way as in
https://github.com/YosysHQ/yosys/pull/5440

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-10-25 23:15:23 +01:00
YRabbit 64700dec65 Gowin. Disable unsupported BSRAM mode in GW5A 
All supported (and planned to be supported) GW5A series chips do not
support the 2: Read-before-Write write mode.

Here, we prohibit the generation of BSRAM with this mode.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-10-23 09:59:56 +01:00
Maxim Kudinov 6535995005 synth_gowin: fix help hint style 2025-10-16 11:09:28 +01:00
Maxim Kudinov 8c347826f6 synth_gowin: make help description more clear 2025-10-16 11:09:28 +01:00
Maxim Kudinov 8f6d63c082 synth_gowin: make setundef an off by default option 2025-10-16 11:09:28 +01:00
YRabbit 02e40e8118 Gowin. Reduce the range of flip-flop types. 
UG303-1.0E_Arora Ⅴ Configurable Function Unit (CFU) User Guide.pdf
specifies that the only flip-flop types supported in GW5 are DFFSE,
DFFRE, DFFPE, and DFFCE.

However, the bit streams generated by the vendor IDE also contain DFF
flip-flops, which are probably the result of optimisation, so we leave
them in the list of permitted items, but add a flag that will allow the
generation of completely correct output files, acceptable for further P&
R using vendor tools (they will not allow the use of flip-flops other
than the four specified in the netlist).

In the GW5 SemiDual Port BSRAM series, the primitive does not have
RESETA and RESETB ports—they are replaced by the RESET port, so we
separate the files for BSRAM generation, especially since in the future
we may have to take into account other, as yet unexplored, differences
in BSRAM.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-10-11 21:12:35 +10:00
Miodrag Milanović 869910055f
Merge pull request #3908 from YosysHQ/ecp5_2_lattice 
synth_ecp5 and synth_nexus to synth_lattice
 2025-10-08 13:07:33 +02:00
Ethan Sifferman d5beb65d30 added SIMLIB_VERILATOR_COMPAT 2025-10-01 10:19:25 -07:00
Miodrag Milanovic 714603bf69 synth_nexus to synth_lattice 2025-09-26 19:45:03 +01:00
Miodrag Milanovic 58f9531bfb enable ABC9 by default except for XO2/3/3D 2025-09-25 15:44:05 +01:00
Miodrag Milanović 4b9e4bfae9 Update techlibs/lattice/synth_lattice.cc 
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
 2025-09-25 15:44:05 +01:00
Miodrag Milanovic faf82a5ff5 Add help message for synth_ecp5 2025-09-25 15:44:05 +01:00
Miodrag Milanovic 47a2215fe0 Update filenames and location for test script 2025-09-25 15:44:05 +01:00
Miodrag Milanovic 4a7f94f1c1 Enable synth_ecp5 wrapper and copy sim files for backwards compatibility 2025-09-25 15:44:05 +01:00
Miodrag Milanovic e7ac237499 Delete synth_ecp5 2025-09-25 15:44:03 +01:00
Miodrag Milanovic cfe53b7395 Move diamond tests 2025-09-25 15:38:57 +01:00
Miodrag Milanovic b94b39cd40 Special DP16KD model is required 2025-09-25 15:38:55 +01:00
Ethan Sifferman 0eb93c80e6 added ifndef SIMLIB_NOCONNECT 2025-09-24 20:50:47 -07:00
Emil J. Tywoniak d30f7847d8 techmap: map $alu to $fa instead of relying on extract_fa 2025-09-23 17:05:12 +02:00
Robert O'Callahan 1e5f920dbd Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
Emil J a78eb9e151
Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort 
write_rtlil: don't sort
 2025-09-22 11:14:39 +02:00
YRabbit d60dc93e92 Gowin. Renaming inputs of the DCS primitive. 
The dynamic clock selection (DCS) primitive has undergone changes with
the release of the GW5A series—the CLK0,1,2,3 inputs are now
CLKIN0,1,2,3, but only for GW5A series chips.

There are no functional changes, only renaming.

Here we are transferring the description of the DCS primitive from
general to specialized files for each chip series.

We have also fixed a bug in the generation script that caused the loss
of primitive parameters. Fortunately, this only affected the
analog-to-digital converter, which has not yet been implemented.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-09-20 16:22:23 +01:00
Jannis Harder 1251e92e3a Add `$input_port` and `$connect` cell types 2025-09-17 13:56:46 +02:00
Robert O'Callahan a7c46f7b4a Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix() 2025-09-16 23:02:16 +00:00