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2522 Commits

Author SHA1 Message Date
Lofty 49f5470b97 analogdevices: double LUT RAM cost 2025-10-21 18:04:01 +01:00
Lofty 5d38d76310 analogdevices: ignore $assert cells 2025-10-20 18:23:25 +01:00
Krystine Sherwin f2b88c23d4 analogdevices: Fixing up bram 
Tested all the accepted configurations in eXpreso, disabling the RBRAM2 configs that fail to place, and increasing the cost for the double site TDP memories.
 2025-10-18 12:14:03 +01:00
Krystine Sherwin 6e5524ee9c analogdevices: Add BRAM options 
Enable `-force-params`, and tidy up lutram mapping too.
 2025-10-18 12:14:01 +01:00
Lofty a119711aac analogdevices: LUT RAM only on positive edge 2025-10-18 12:11:18 +01:00
Lofty f1579304a6 analogdevices: DSP tweaks 2025-10-18 12:10:50 +01:00
Lofty 059925a56a analogdevices: DSP inference 2025-10-16 23:33:59 +01:00
Lofty aab52403f1 analogdevices: remove cells_xtra 2025-10-16 09:27:15 +01:00
Lofty d43f6f7274 analogdevices: timings for t40lp 2025-10-16 08:43:08 +01:00
Lofty 6d0c2fe048 analogdevices: use single tech param 2025-10-16 08:43:08 +01:00
Lofty 7e894d4159 analogdevices: expreso does not care about clock buffers 2025-10-16 08:43:08 +01:00
Lofty 9cfa5fb369 analogdevices: prepare for t40lp timings 2025-10-16 08:43:08 +01:00
Krystine Sherwin 151f530677 analogdevices: Adding RBRAM2 and -tech 2025-10-16 08:43:08 +01:00
Krystine Sherwin edeb6128ab analogdevices: (some) Native BRAM 
Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
 2025-10-16 08:43:08 +01:00
Krystine Sherwin 18a4e44b28 analogdevices: Native LUTRAM primitives 2025-10-16 08:43:08 +01:00
Lofty b3e3614c96 analogdevices: LUTRAM config 2025-10-16 08:43:08 +01:00
Lofty 0bec90930f analogdevices: update timing model 2025-10-16 08:43:08 +01:00
Lofty b8254b96c7 analogdevices: user retargeting 2025-10-16 08:43:08 +01:00
Lofty 799a4e4291 analogdevices: more housekeeping 2025-10-16 08:43:08 +01:00
Lofty c7580131ad analogdevices: remove some extra cells! 2025-10-16 08:43:08 +01:00
Lofty 2cdd97a8d4 test suite 2025-10-16 08:43:08 +01:00
Lofty 04fd4d4601 synth_analogdevices: remove scopeinfo cells 2025-10-16 08:43:08 +01:00
Lofty 7878a7e2bd Create synth_analogdevices 2025-10-16 08:43:08 +01:00
YRabbit 02e40e8118 Gowin. Reduce the range of flip-flop types. 
UG303-1.0E_Arora Ⅴ Configurable Function Unit (CFU) User Guide.pdf
specifies that the only flip-flop types supported in GW5 are DFFSE,
DFFRE, DFFPE, and DFFCE.

However, the bit streams generated by the vendor IDE also contain DFF
flip-flops, which are probably the result of optimisation, so we leave
them in the list of permitted items, but add a flag that will allow the
generation of completely correct output files, acceptable for further P&
R using vendor tools (they will not allow the use of flip-flops other
than the four specified in the netlist).

In the GW5 SemiDual Port BSRAM series, the primitive does not have
RESETA and RESETB ports—they are replaced by the RESET port, so we
separate the files for BSRAM generation, especially since in the future
we may have to take into account other, as yet unexplored, differences
in BSRAM.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-10-11 21:12:35 +10:00
Miodrag Milanović 869910055f
Merge pull request #3908 from YosysHQ/ecp5_2_lattice 
synth_ecp5 and synth_nexus to synth_lattice
 2025-10-08 13:07:33 +02:00
Ethan Sifferman d5beb65d30 added SIMLIB_VERILATOR_COMPAT 2025-10-01 10:19:25 -07:00
Miodrag Milanovic 714603bf69 synth_nexus to synth_lattice 2025-09-26 19:45:03 +01:00
Miodrag Milanovic 58f9531bfb enable ABC9 by default except for XO2/3/3D 2025-09-25 15:44:05 +01:00
Miodrag Milanović 4b9e4bfae9 Update techlibs/lattice/synth_lattice.cc 
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
 2025-09-25 15:44:05 +01:00
Miodrag Milanovic faf82a5ff5 Add help message for synth_ecp5 2025-09-25 15:44:05 +01:00
Miodrag Milanovic 47a2215fe0 Update filenames and location for test script 2025-09-25 15:44:05 +01:00
Miodrag Milanovic 4a7f94f1c1 Enable synth_ecp5 wrapper and copy sim files for backwards compatibility 2025-09-25 15:44:05 +01:00
Miodrag Milanovic e7ac237499 Delete synth_ecp5 2025-09-25 15:44:03 +01:00
Miodrag Milanovic cfe53b7395 Move diamond tests 2025-09-25 15:38:57 +01:00
Miodrag Milanovic b94b39cd40 Special DP16KD model is required 2025-09-25 15:38:55 +01:00
Ethan Sifferman 0eb93c80e6 added ifndef SIMLIB_NOCONNECT 2025-09-24 20:50:47 -07:00
Emil J. Tywoniak d30f7847d8 techmap: map $alu to $fa instead of relying on extract_fa 2025-09-23 17:05:12 +02:00
Robert O'Callahan 1e5f920dbd Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
Emil J a78eb9e151
Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort 
write_rtlil: don't sort
 2025-09-22 11:14:39 +02:00
YRabbit d60dc93e92 Gowin. Renaming inputs of the DCS primitive. 
The dynamic clock selection (DCS) primitive has undergone changes with
the release of the GW5A series—the CLK0,1,2,3 inputs are now
CLKIN0,1,2,3, but only for GW5A series chips.

There are no functional changes, only renaming.

Here we are transferring the description of the DCS primitive from
general to specialized files for each chip series.

We have also fixed a bug in the generation script that caused the loss
of primitive parameters. Fortunately, this only affected the
analog-to-digital converter, which has not yet been implemented.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-09-20 16:22:23 +01:00
Jannis Harder 1251e92e3a Add `$input_port` and `$connect` cell types 2025-09-17 13:56:46 +02:00
Robert O'Callahan a7c46f7b4a Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix() 2025-09-16 23:02:16 +00:00
Robert O'Callahan 5ac6858f26 Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
Emil J. Tywoniak 73747f6928 read_verilog: add -relativeshare for synthesis reproducibility testing 2025-09-16 15:47:35 +02:00
Robert O'Callahan 1a367b907c Use fast path for 32-bit Const integer constructor in more places 2025-09-16 03:17:24 +00:00
Robert O'Callahan 09b493cfcd Update techlibs to avoid bits() 2025-09-16 03:17:23 +00:00
Robert O'Callahan e0ae7b7af4 Remove .c_str() calls from log()/log_error() 
There are some leftovers, but this is an easy regex-based approach that removes most of them.
 2025-09-11 20:59:37 +00:00
Robert O'Callahan c7df6954b9 Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00
N. Engelhardt 15d24bf2e6 synth_quicklogic: add -noflatten option 2025-08-25 17:25:58 +02:00
Miodrag Milanović c7e6275d0d
Merge pull request #5045 from danderson/push-nwpulrqymkqp 
techlibs/lattice: add missing clock muxes to ECP5 block ram blackboxes
 2025-08-25 15:28:34 +02:00