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2189 Commits

Author SHA1 Message Date
Robert O'Callahan 3a5742ffd2 Improve commutative hashing. 
The simple XOR `commutative_eat()` implementation produces a lot of collisions.
https://www.preprints.org/manuscript/201710.0192/v1/download is a useful reference on this topic.

Running the included `hashTest.cc` without the hashlib changes, I get 49,580,349 collisions.
The 49,995,000 (i,j) pairs (0 <= i < 10000, i < j < 10000) hash into only 414,651 unique hash values.
We get simple collisions like (0,1) colliding with (2,3).

With the hashlib changes, we get only 707,099 collisions and 49,287,901 unique hash values.
Much better! The `commutative_hash` implementation corresponds to `Sum(4)` in the paper
mentioned above.
 2025-08-19 21:45:52 +00:00
Anhijkt e1276560cd opt_dff: add another test 2025-08-19 23:48:45 +03:00
Emil J b0d709f6cf
Merge pull request #5294 from rocallahan/precision-tests 
Add tests for dynamic precision and with with an int parameter
 2025-08-19 16:42:49 +02:00
Emil J. Tywoniak 7ee62c832b bitpattern: unit test 2025-08-18 19:57:45 +02:00
Jannis Harder 7c409e2d5a
Merge pull request #5285 from jix/abstract_initstates 
abstract: Add -initstates option
 2025-08-18 15:39:09 +02:00
KrystalDelusion 6d55ca204b
Merge pull request #5281 from suisseWalter/add_parameterised_cells_stat 
STAT: Add parameterised cells
 2025-08-18 09:21:45 +12:00
clemens 9278bed853 removed copyright notice on lib file. 
Should be covered by the yosys license not  anything else.
 2025-08-16 09:40:03 +02:00
clemens 73d1177665 testcases 
one testcase for single parameter cells.
one testcase for double parameter cells.
 2025-08-16 09:40:03 +02:00
clemens d8fb4da437 updated testcase 2025-08-16 09:32:08 +02:00
Robert O'Callahan e906ea3f1b Add tests for dynamic precision and with with an int parameter 2025-08-15 23:58:58 +00:00
Krystine Sherwin ec18d1aede
rename.cc: Fixup ports after -unescape 2025-08-15 10:48:32 +12:00
Emil J 195d3ef940
Merge pull request #5100 from jix/rename_move_to_cell 
rename: add -move-to-cell option in -wire mode
 2025-08-14 16:45:33 +02:00
Anhijkt e486994f60 opt_dff: add test 2025-08-14 00:13:23 +03:00
clemens 71307b4a51 add Testcases 
Fix existing testcases
Fix edgecase where modules where counted as cells.
 2025-08-13 14:46:01 +02:00
Jannis Harder 77089a8d03 rename: add -move-to-cell option in -wire mode 2025-08-13 11:11:52 +02:00
Jannis Harder 1f876f3a22 abstract: Add -initstates option 2025-08-12 15:37:12 +02:00
Emil J. Tywoniak 6042ae0e8a simplify: add smoke test for system function calls 2025-08-12 12:59:31 +02:00
KrystalDelusion 1ae82d7b9d
Merge pull request #5233 from YosysHQ/krys/equiv_assume 
Assumptions for equiv_*
 2025-08-09 10:39:04 +12:00
Emil J d68d28d05e
Merge pull request #5183 from YosysHQ/emil/test-diagnostics 
logger: add -expect types prefix-log, prefix-warning, prefix-error
 2025-08-08 14:46:25 +02:00
KrystalDelusion 7f0e864d44
Merge pull request #5265 from bhagwat-rahul/fix-package-import 
Support package import
 2025-08-08 09:32:54 +12:00
Emil J 1e58443397
Merge pull request #5264 from YosysHQ/krys/raise_error_always 
raise_error: Add -always
 2025-08-07 11:43:04 +02:00
Rahul Bhagwat 5cc1365b32
add newline - whitespace 2025-08-06 19:00:11 -04:00
Rahul Bhagwat d3c8e6c14c
use more standard naming conventions 2025-08-06 15:39:30 -04:00
Rahul Bhagwat 7e0157ba2b
fix whitespace issues 2025-08-06 15:32:36 -04:00
Emil J 8576d2d147
Merge pull request #5263 from rocallahan/stringf-width 
Making `stringf()` use the format conversion specs as-is without widening them
 2025-08-06 11:36:28 +02:00
Krystine Sherwin af7d1d3f4f
cutpoint_blackbox.ys: Extra edge case 2025-08-06 18:11:35 +12:00
Krystine Sherwin 1bf9530fcc
cutpoint_blackbox.ys: Add verific-style unknown module 2025-08-06 16:51:14 +12:00
Krystine Sherwin f9e8127e2b
tests: Add equiv_induct to equiv_assume.ys 2025-08-06 15:13:04 +12:00
Lofty 7537a49f0d
Merge pull request #5241 from Anhijkt/opt_dff-simplify-pt 
opt_dff: implement simplify_patterns
 2025-08-04 09:44:57 +01:00
Rahul Bhagwat 761015b23e
add separate module test 2025-08-03 23:48:33 -04:00
Krystine Sherwin f78cd9d13f
raise_error: Extra test 2025-08-02 14:54:32 +12:00
Krystine Sherwin 895dfd963f
raise_error: Add -always 2025-08-02 14:53:36 +12:00
Robert O'Callahan ffd52a0d8e Making `stringf()` use the format conversion specs as-is without widening them. 
And make sure our fast-path for `%d` and `%u` narrows to `int` correctly.

Resolves #5260
 2025-07-31 10:54:56 +00:00
KrystalDelusion a18acaca82
Merge pull request #5068 from YosysHQ/krys/bugpoint_fixes 
Updates to bugpoint
 2025-07-30 10:05:22 +12:00
Krystine Sherwin fe07d390f1
tests/bugpoint: More tests 
More coverage.
 2025-07-29 11:39:52 +12:00
Krystine Sherwin 93f7429f4f
tests: Add bugpoint to MK_TEST_DIRS 
Also change `-err_grep` to `-err-grep` for consistency with `-expect-return`.
 2025-07-29 11:39:51 +12:00
Krystine Sherwin b5a13ae95b
bugpoint.cc: Rename to -err_grep 2025-07-29 11:39:51 +12:00
Krystine Sherwin fb92eabdcd
bugpoint: Add -greperr option 
`-greperr <string>` redirects stderr to 'bugpoint-case.err', and then searches that file for `<string>`.
Move `-runner` option up with the other options to reduce ambiguity (i.e. so it doesn't look like it's another design parts constraint).
Also some shuffling of `err.ys`.
 2025-07-29 11:39:51 +12:00
Krystine Sherwin 8d5dbae06e
raise_error.cc: Option for direct to stderr 
Add more to help text to describe usage.
Add test for no value (should `exit(1)`).
 2025-07-29 11:39:50 +12:00
Krystine Sherwin 134da811f7
Add raise_error pass 
Raise errors from attributes for testing.
I want it for bugpoint tests but it could be useful elsewhere.
 2025-07-29 11:39:50 +12:00
Robert O'Callahan 8b75c06141 Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
Anhijkt ca8af1f8c8 opt_dff: implement simplify_patterns 2025-07-21 14:15:26 +03:00
KrystalDelusion 5b8b5292ee
Merge pull request #4959 from YosysHQ/krys/primitive_array_error 
simplify: Skip AST_PRIMITIVE in AST_CELLARRAY
 2025-07-21 10:26:00 +12:00
Martin Povišer 9ab1946799
Merge pull request #5209 from povik/hieropt 
Start `opt_hier` to enable hierarchical optimization
 2025-07-17 14:12:18 +02:00
N. Engelhardt d009bcc9b6
Merge pull request #5198 from YosysHQ/nak/lcov 2025-07-17 11:57:58 +02:00
N. Engelhardt fb6974dcd7 print summary of line coverage to log 2025-07-16 13:40:07 +02:00
Krystine Sherwin 5ec189a2f5
Tests: Extra equiv_assume tests 2025-07-16 21:06:04 +12:00
Krystine Sherwin d30f934d0d
equiv_simple: Add -set-assumes option 
Based on existing code for input cone and the `sat` handling of `-set-assumes`.
Update `equiv_assume.ys` to use `-set-assumes` option.
 2025-07-16 21:04:41 +12:00
Krystine Sherwin a57c593c41
tests: Add equiv_assume.ys 2025-07-16 15:32:47 +12:00
Emil J. Tywoniak c7a3abbcc4 libparse: LibertyExpression unit test 2025-07-15 12:53:30 +02:00
Emil J. Tywoniak e960428587 unit tests: fix run failure detection 2025-07-15 12:21:01 +02:00
Emil J. Tywoniak 6ee01308f2 dfflibmap: show dffe inference is broken by space ANDs 2025-07-11 00:33:01 +02:00
Emil J 14aad097f0
Merge pull request #5190 from YosysHQ/emil/dfflibmap-fix-negated-next_state 
dfflibmap: propagate negated next_state to output correctly
 2025-07-10 19:50:02 +02:00
Emil J. Tywoniak 7fe817c52f dfflibmap: test negated state next_state with mixed polarities 2025-07-10 18:54:43 +02:00
N. Engelhardt 02323295b0
Merge pull request #5179 from YosysHQ/krys/assert2cover 2025-07-10 14:53:22 +02:00
Emil J 66035f706e
Merge pull request #5177 from YosysHQ/emil/rename-unescape 
rename: add -unescape
 2025-07-08 10:45:11 +02:00
Martin Povišer 22a44e4333 Start `opt_hier` 2025-07-05 16:45:52 +02:00
Gary Wong 5feb1a1752 verilog: add support for SystemVerilog string literals. 
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
 2025-07-03 20:51:12 -06:00
N. Engelhardt 8a4f465143 update test to use suggested selection for assertions 2025-07-01 11:46:27 +02:00
Krystine Sherwin 017524d7a2
tests/verific: Don't ASAN verific 2025-06-28 11:33:18 +12:00
N. Engelhardt ef3f541501 add linecoverage command to generate lcov report from selection 2025-06-26 13:21:53 +02:00
Emil J. Tywoniak 2b659626a3 rename: add -unescape 2025-06-24 12:33:33 +02:00
Emil J. Tywoniak 73cbcffbbb fixup! dfflibmap: propagate negated next_state to output correctly 2025-06-24 12:31:30 +02:00
Emil J. Tywoniak 778079b058 dfflibmap: propagate negated next_state to output correctly 2025-06-24 12:01:12 +02:00
George Rennie 170933ecb0
Merge pull request #5165 from georgerennie/george/opt_dff_uaf 
opt_dff: don't remove cells until all have been visited to prevent UAF
 2025-06-20 23:33:26 +01:00
garytwong 834a7294b7
verilog: fix string literal regular expression (#5187) 
* verilog: fix string literal regular expression.

A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.

* verilog: add regression test for string literal regex bug.

Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af and fixed by 40aa7eaf).
 2025-06-19 12:41:18 -04:00
Emil J. Tywoniak 4276756f32 fixup! const2ast: add diagnostics tests 2025-06-16 22:50:31 +02:00
Emil J. Tywoniak 49cd3887a7 const2ast: add diagnostics tests 2025-06-16 21:48:12 +02:00
Krystine Sherwin fa68299b25
tests/verific: Add chformal tests 2025-06-14 11:06:38 +12:00
Krystine Sherwin 45131f4425
chformal: Add -assert2cover option 
Also add to chformal tests.
 2025-06-14 10:54:23 +12:00
KrystalDelusion 82888580ac
Merge pull request #5152 from garytwong/unique-if 
verilog: implement SystemVerilog unique/unique0/priority if semantics.
 2025-06-13 09:56:53 +12:00
Emil J c0f52c6ead
Merge pull request #5167 from YosysHQ/emil/fix-splitnets-single-bit-vector 
splitnets: handle single-bit vectors consistently
 2025-06-11 22:47:48 +02:00
George Rennie 7160c91800 tests: add test for #5164 opt_dff -sat UAF 2025-06-06 23:46:23 +01:00
Emil J. Tywoniak 239c265093 splitnets: handle single-bit vectors consistently 2025-06-05 10:58:06 +02:00
George Rennie 0fcf5c080d
Merge pull request #5158 from georgerennie/george/task_inout 
read_verilog/astsimplify: copy inout ports in and out of functions/tasks
 2025-06-04 14:23:08 +01:00
George Rennie ab40403d90
Merge pull request #5154 from georgerennie/george/post_incdec_undo_fix 
read_verilog: fix -1 constant used to correct post increment/decrement
 2025-06-04 14:22:32 +01:00
Emil J c21cd300a0
Merge pull request #5109 from YosysHQ/emil/aiger-map-fix-outputs 
aiger: fix -map and -vmap
 2025-06-02 15:07:19 +02:00
George Rennie 97f51bb4b7 tests: add tests for task/function argument input/output copying 2025-05-31 01:21:06 +01:00
KrystalDelusion 545753cc5a
Merge pull request #5143 from YosysHQ/krys/typedef_struct_global 
SystemVerilog: Fix typedef struct in global space
 2025-05-31 09:59:26 +12:00
George Rennie 3790be114f tests: add tests for verilog pre/post increment/decrement in expressions 2025-05-30 14:38:25 +01:00
Gary Wong 7b09dc31af tests: add cases covering full_case and parallel_case semantics 
This is @KrystalDelusion's suggestion in PR #5141 to verify
sensible implementation of all 4 possible full_case/parallel_case
combinations.

(Also including two similar tests to check the Verilog frontend
applies the correct attributes when given SystemVerilog
priority/unique case and if statements.)
 2025-05-29 20:45:57 -06:00
George Rennie 3ef4c91c31
Merge pull request #5148 from georgerennie/george/convertible_to_int_fix 
Fix convertible_to_int handling of 32 bit unsigned ints with MSB set.
 2025-05-29 10:33:12 +01:00
KrystalDelusion 489a12d6c1
Merge pull request #5141 from garytwong/unique-if 
Accept (and ignore) SystemVerilog unique/priority if.
 2025-05-27 09:45:50 +12:00
George Rennie 353fd0f7f4 tests: test opt_expr for 32 bit unsigned shifts 2025-05-26 15:28:44 +01:00
Krystine Sherwin 995a893afd
Tests: Add svtypes/typedef_struct_global.ys 2025-05-26 12:16:58 +12:00
Gary Wong 73e45d29d6 Add semantic test cases for SystemVerilog priority/unique/unique0 "if". 
The tests/verilog/*_if_enc.ys scripts instantiate simple encoder
modules, both with and without the SystemVerilog priority/unique/unique0
keywords, and check for consistency between the two for the subset
of inputs where the priority/unique/unique0 "if" result is
well-defined.

These tests vacuously succeed at the moment, since priority/unique
keywords are silently ignored and therefore the generated logic is
trivially identical.  But the test cases will be capable of detecting
certain types of unsound optimisation if priority/unique handling is
introduced later.
 2025-05-24 08:44:04 -06:00
Emil J 18abf2d4f7
Merge pull request #5138 from YosysHQ/emil/libcache-verbose 
libcache: add -quiet and -verbose
 2025-05-24 00:05:46 +02:00
Emil J 4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width 
rtlil: enable single-bit vector wires
 2025-05-23 15:55:45 +02:00
Gary Wong 9770ece187 Accept (and ignore) SystemVerilog unique/priority if. 
Add support to the "read_verilog -sv" parser to validate the
"unique", "unique0", and "priority" keywords in contexts where
they're legal according to 1800-2012 12.4.2.

This affects only the grammar accepted; the behaviour of conditionals
is not changed.  (But accepting this syntax will provide scope for
possible optimisations as future work.)

Three test cases ("unique_if", "unique_if_else", and
"unique_if_else_begin") verify that the keywords are accepted where
legal and rejected where illegal, as described in the final paragraph
of 12.4.2.
 2025-05-22 19:28:28 -06:00
George Rennie 6331f92d00
Merge pull request #5101 from georgerennie/george/opt_expr_shift_ovfl 
opt_expr: fix shift optimization with overflowing shift amount
 2025-05-22 15:16:19 +01:00
KrystalDelusion 4c72b0ecd8
Merge pull request #5116 from YosysHQ/krys/update_fst 
Update fstlib
 2025-05-16 09:22:52 +12:00
KrystalDelusion f7888c607b
Merge pull request #5089 from YosysHQ/krys/cutpoint_whole 
cutpoint: Re-add whole module optimization
 2025-05-16 09:22:28 +12:00
Emil J 3823157c25
Merge pull request #5080 from akashlevy/muldiv_c 
Add `muldiv_c` peepopt
 2025-05-15 11:03:25 +02:00
Emil J. Tywoniak e5171d6aa1 verific: support single_bit_vector 2025-05-12 13:23:29 +02:00
Emil J. Tywoniak 5e72464a15 rtlil: enable single-bit vector wires 2025-05-12 13:23:29 +02:00
Krystine Sherwin afd5bbc7fa
fstdata.cc: Fix last step 
Includes test file for sanity checking simulation steps.
 2025-05-12 13:18:19 +12:00
Adrien Prost-Boucle 6bf7587338 URAM mapping : Add test for 2048 x 144b 2025-05-10 14:53:56 +02:00
Emil Jiří Tywoniak cbf069849e aiger: add regression test for sliced output segfault 2025-05-09 16:01:47 +02:00
Emil J. Tywoniak 9d2f9f7557 libcache: fix test 2025-05-09 12:40:38 +02:00
George Rennie d59380b3a0 tests: more complete testing of shift edgecases 2025-05-08 11:09:01 +02:00