6 Commits

Author	SHA1	Message	Date
Claire Xenia Wolf	72787f52fc	Fixing old e-mail addresses and deadnames ... s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;	2021-06-08 00:39:36 +02:00
Marcelina Kościelnicka	aee439360b	Add force_downto and force_upto wire attributes. ... Fixes #2058.	2020-05-19 01:42:40 +02:00
Clifford Wolf	151db528e4	Fix missing newline at end of file ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-22 18:09:37 +02:00
Miodrag Milanovic	5f561bdcb1	Proper arith for Anlogic and use standard pass	2019-08-12 20:21:36 +02:00
Miodrag Milanovic	837cb0a1b9	anlogic : Fix alu mapping	2019-08-03 14:47:33 +02:00
Miodrag Milanovic	83bce9f59c	Initial support for Anlogic FPGA	2018-12-01 18:28:54 +01:00