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2476 Commits

Author SHA1 Message Date
Robert O'Callahan e0ae7b7af4 Remove .c_str() calls from log()/log_error() 
There are some leftovers, but this is an easy regex-based approach that removes most of them.
 2025-09-11 20:59:37 +00:00
Robert O'Callahan c7df6954b9 Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00
N. Engelhardt 15d24bf2e6 synth_quicklogic: add -noflatten option 2025-08-25 17:25:58 +02:00
Miodrag Milanović c7e6275d0d
Merge pull request #5045 from danderson/push-nwpulrqymkqp 
techlibs/lattice: add missing clock muxes to ECP5 block ram blackboxes
 2025-08-25 15:28:34 +02:00
Robert O'Callahan 8b75c06141 Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
Martin Povišer 9ab1946799
Merge pull request #5209 from povik/hieropt 
Start `opt_hier` to enable hierarchical optimization
 2025-07-17 14:12:18 +02:00
Martin Povišer 415b7d3f65 Drop experimental label off `synth -hieropt` 2025-07-17 12:02:44 +02:00
Martin Povišer 22a44e4333 Start `opt_hier` 2025-07-05 16:45:52 +02:00
YRabbit 85e7c68fc6 Gowin. BUGFIX. Fix multi-line descriptions. 
If let's say the enumeration of inputs took several lines, then all
after the first one were ignored. Since the first line ended with a
comma, an error was generated when trying to use the resulting file.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-07-02 12:39:18 +10:00
KrystalDelusion 5268565410
Merge pull request #5108 from marzoul/adrien-uram 
Create a single-port URAM mapping to support memories 2048 x 144b
 2025-05-13 09:54:36 +12:00
Adrien Prost-Boucle 6bf7587338 URAM mapping : Add test for 2048 x 144b 2025-05-10 14:53:56 +02:00
Adrien Prost-Boucle c7de531231 URAM mapping : Fix port indexes according to Yosys warnings 2025-05-09 15:09:11 +02:00
Adrien Prost-Boucle c4a49f0c55 Create a single-port URAM mapping to support memories 2048 x 144b 2025-05-09 14:16:03 +02:00
Patrick Urban 6d575918fc gatemate: Set unused BRAM inputs to 'bx 
This will reduce the number of CPEs to generate fixed values at the block RAM inputs, if it is not used.
 2025-04-28 14:42:16 +02:00
KrystalDelusion 2d6255175e
Merge pull request #5057 from secworks/blocking_assignment_greenpak4_cells_sim_digital 
Change to use blocking assignments in non-clocked processes.
 2025-04-26 11:15:10 +12:00
KrystalDelusion 6564810ae3
Merge pull request #4992 from Anhijkt/fix-ice40dsp-unsigned 
ice40_dsp: fix const handling
 2025-04-26 11:15:02 +12:00
Miodrag Milanović febc07e6fb
Merge pull request #5039 from YosysHQ/gatemate_bram 
gatemate: WRITE_THROUGH mode change
 2025-04-25 09:53:43 +02:00
Emil J f8c027b70e
Merge pull request #5056 from secworks/blocking_assignment_gatemate_cells_sim 
Change to blocking assignments in non-clocked process.
 2025-04-23 23:13:54 +02:00
Joachim Strömbergson 2fcb61adb5
Change to use blocking assignments in non-clocked processes. 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2025-04-23 17:21:32 +02:00
Joachim Strömbergson 90f50722ab
Change to blocking assignments in non-clocked process. 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2025-04-23 17:13:37 +02:00
Joachim Strömbergson e4d6781088
Changing non clocked alway assignment to blocking. 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
 2025-04-23 16:59:53 +02:00
David Anderson af8e85b7d2 techlibs/lattice: add missing clock muxes to ECP5 block ram blackboxes 
prjtrellis documentation shows that EBR clock inputs have optional inverters.
The bram techmap outputs those parameters, and nextpnr consumes them. But for
whatever reason, Diamond doesn't include those parameters in its blackbox
models. This makes synth_lattice fail when targeting ECP5 with a design that
maps block RAMs if you include any pass that needs cells_bb_ecp5.v's definitions.

This change fixes up the ECP5 bram blackbox models at generation time, by
adding the missing parameters back in.

Signed-off-by: David Anderson <dave@natulte.net>
 2025-04-21 11:57:49 -07:00
Miodrag Milanovic c343462c16 gatemate: WRITE_THROUGH mode change 2025-04-18 14:16:02 +02:00
Anhijkt 163e339c69 ice40_dsp: add unextend_unsigned function 2025-04-11 19:41:35 +03:00
Anhijkt 4a178d7cff ice40_dsp: change unextend call condition 2025-04-10 17:42:39 +03:00
Adrien Prost-Boucle 3911a627a8 Clearer diff for the all-x corner case 2025-04-07 07:55:30 +02:00
Adrien Prost-Boucle 7a1729e609 Fix mux xilinx mapping when all inputs are x 2025-04-06 11:43:17 +02:00
Anhijkt 2b3a148fc4 ice40_dsp: fix const handling 2025-04-05 13:46:38 +03:00
Emil J 1b25e1cee0
Merge pull request #4942 from Anhijkt/fix-ice40dsp 
ice40_dsp: fix log_assert issue
 2025-03-28 13:32:17 +01:00
YRabbit c37db637c7 Gowin. Remove unnecessary modules 
Primitives that are not planned for implementation for reasons of
belonging to old unsupported chips or representing composite complex IPs
rather than primitives are removed.
Also latches and large MUXes not planned for implementation.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-03-28 06:34:26 +10:00
Scott Ashcroft 04bbd4e7e2 Make all vector-size related integer params in $print sim model signed 
This fixes iverilog crashes on 32-bit, similar to 95944eb for $mem.
 2025-03-25 13:08:49 +00:00
Miodrag Milanović 733487e730
Merge pull request #4950 from pu-cc/gatemate-serdes-update 
gatemate: Add `CC_SERDES` parameters and update port names
 2025-03-20 10:52:23 +01:00
Anhijkt a9d765e11e ice40_dsp: group empty wires 2025-03-16 15:11:45 +02:00
Anhijkt 725c489c7e ice40_dsp: fix log_assert issue 2025-03-15 17:11:32 +02:00
Martin Povišer 6da543a61a
Merge pull request #4818 from povik/macc_v2 
Add `$macc_v2`
 2025-03-12 22:55:40 +01:00
KrystalDelusion bf96ed322d
Merge pull request #4827 from aerkiaga/main 
Update ALU MULT mode in gowin to match nextpnr
 2025-03-13 10:49:37 +13:00
Martin Povišer d8a4991289
Merge pull request #4931 from povik/buf-clean 
opt_clean, simplemap: Add `$buf` handling
 2025-03-10 15:10:17 +01:00
Martin Povišer 9f7cdd4bd4
Merge pull request #4262 from RoaLogic/master 
MAX10 updates
 2025-03-07 19:59:55 +01:00
Martin Povišer 557047fe1e opt_clean, simplemap: Add `$buf` handling 2025-03-07 16:08:38 +01:00
N. Engelhardt 268a034b21
Merge pull request #4866 from YosysHQ/ql_ioff 
add IOFF inference for qlf_k6n10f
 2025-03-03 14:12:09 +00:00
N. Engelhardt 303a386ecc create duplicate IOFFs if multiple output ports are connected to the same register 2025-01-31 11:28:57 +01:00
Krystine Sherwin 0ec5f1b756
pmgen: Move passes out of pmgen folder 
- Techlib pmgens are now in relevant techlibs/*.
- `peepopt` pmgens are now in passes/opt.
- `test_pmgen` is still in passes/pmgen.
- Update `Makefile.inc` and `.gitignore` file(s) to match new `*_pm.h` location,
  as well as the `#include`s.
- Change default `%_pm.h` make target to `techlibs/%_pm.h` and move it to the
  top level Makefile.
- Update pmgen target to use `$(notdir $*)` (where `$*` is the part of the file
  name that matched the '%' in the target) instead of `$(subst _pm.h,,$(notdir
  $@))`.
 2025-01-31 15:18:28 +13:00
N. Engelhardt 25b400982b detect aliased I/O ports 2025-01-28 17:37:23 +01:00
N. Engelhardt 9da4fe747e fix bus ioff inference 2025-01-28 11:23:36 +01:00
Martin Povišer 6c76dcec3e macc_v2: Fix v2 omissions 2025-01-27 13:08:44 +01:00
N. Engelhardt 1cf8e7c7db add ioff inference for qlf_k6n10f 2025-01-24 21:17:15 +01:00
Martin Povišer 3184b335da macc_v2: Fix language constructs in simlib model 2025-01-24 13:22:30 +01:00
Martin Povišer 1e8aa56f7f macc_v2: Init simlib model 2025-01-24 12:38:03 +01:00
Emil J. Tywoniak a58481e9b7 mark all hash_into methods nodiscard 2025-01-14 12:39:15 +01:00
Emil J 9f7040b3d1
Merge pull request #4683 from keszybz/use-SOURCE_DATE_EPOCH 
Respect $SOURCE_DATE_EPOCH in generate_bram_types_sim.py
 2025-01-10 23:43:26 +01:00