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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-22 06:07:26 +02:00
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17,138 Commits 140 Branches 70 Tags
gus/read-verilog-signedness-bugs
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4 Commits
Author SHA1 Message Date
Emil J. Tywoniak f213a34427 Remove FHS dependency by replacing /bin/bash with /usr/bin/env bash everywhere 2026-04-22 10:39:19 +02:00
dh73 acee813a5c Fixed the -vout flag to -vqm in examples/intel directory 2017-11-14 22:55:48 -06:00
Larry Doolittle 2021ddecb3 Squelch trailing whitespace 2017-04-12 15:11:09 +02:00
dh73 c27dcc1e47 Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs 2017-04-05 23:01:29 -05:00
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