luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-22 06:07:26 +02:00
Code Issues Packages Projects Releases Wiki Activity
15,963 Commits 140 Branches 70 Tags
emil/stub-sdc-interpreter
Commit Graph
1 Commits
Author SHA1 Message Date
Ruben Undheim 397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00