luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-22 06:07:26 +02:00
Code Issues Packages Projects Releases Wiki Activity
15,305 Commits 140 Branches 70 Tags
emil/segfault-command
Commit Graph
5 Commits
Author SHA1 Message Date
Lofty 8cc9aa7fc6 intel_alm: drop quartus support 2024-05-03 11:32:33 +01:00
gatecat eb106732d9 intel_alm: Add global buffer insertion 
Signed-off-by: gatecat <[email protected]>
 2021-05-15 22:37:06 +01:00
gatecat 5dba138c87 intel_alm: Add IO buffer insertion 
Signed-off-by: gatecat <[email protected]>
 2021-05-15 22:37:06 +01:00
Dan Ravensloft 0d4c2f0a65 intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
Dan Ravensloft 2e37e62e6b synth_intel_alm: alternative synthesis for Intel FPGAs 
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
 2020-04-15 11:40:41 +02:00