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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-22 06:07:26 +02:00
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14,456 Commits 140 Branches 70 Tags
emil/repro-test-dffe-dfflibmap
Commit Graph
9 Commits
Author SHA1 Message Date
Miodrag Milanovic 19da7f7d59 Update makefile to make options uniform 2024-06-17 13:29:11 +02:00
Miodrag Milanovic f536de0e0e Verific support for VHDL 2019 2024-03-28 13:21:55 +01:00
Miodrag Milanovic 17269ae59b Option to disable verific VHDL support 2021-10-20 10:02:58 +02:00
Clifford Wolf 5fa2aa2741 Move Verific SVA importer to extra C++ source file
Signed-off-by: Clifford Wolf <[email protected]>
2018-02-18 13:52:49 +01:00
Clifford Wolf 675f53abbb Fix permissions on verific vdb files 2018-01-28 18:52:01 +01:00
Clifford Wolf b18f3a2974 Changes for Verific 3.16_484_32_151112 2015-11-12 19:28:14 +01:00
Clifford Wolf 7661ded8dd Fixed verific bindings for new RTLIL api 2014-07-27 12:00:28 +02:00
Clifford Wolf 6a53bc7b27 Copy Verific vdbs files to Yosys "share" data directory 2014-03-13 17:34:31 +01:00
Clifford Wolf 8d06f9f2fe Added "verific" command 2014-03-09 20:40:04 +01:00
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