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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-22 06:07:26 +02:00
Code Issues Packages Projects Releases Wiki Activity
14,053 Commits 140 Branches 70 Tags
emil/log-deprecated-temp
Commit Graph
110 Commits
Author SHA1 Message Date
Clifford Wolf 1e67099b77 Added $assert cell 2014-01-19 14:03:40 +01:00
Clifford Wolf 3d7a1491aa Fixed $lut simlib model for a wider range of tools 2014-01-18 19:31:40 +01:00
Clifford Wolf 2fbaaaca7a More changes to simlib to make it friendlier to a wider range of tools 2014-01-18 19:13:43 +01:00
Clifford Wolf 4a9e133fab Fixed a type in $mem model in simlib.v 2014-01-18 18:54:50 +01:00
Clifford Wolf 5b96675696 Added $bu0 cell to simlib.v 2014-01-18 15:35:15 +01:00
Clifford Wolf 369bf81a70 Added support for non-const === and !== (for miter circuits) 2013-12-27 14:20:15 +01:00
Clifford Wolf 1afe6589df Renamed stdcells_sim.v to simcells.v and fixed blackbox.v 2013-11-24 20:44:00 +01:00
Clifford Wolf e5b974fa2a Cleanups and bugfixes in response to new internal cell checker 2013-11-11 00:39:45 +01:00
Clifford Wolf 5998c101a4 Added $sr, $dffsr and $dlatch cell types 2013-10-18 11:56:16 +02:00
Clifford Wolf 288ba9618a Moved common techlib files to techlibs/common 2013-09-15 11:52:57 +02:00
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