3 Commits

Author	SHA1	Message	Date
Miodrag Milanovic	48a3dcc02a	End of file fix	2026-06-23 07:23:41 +02:00
Udi Finkelstein	73d426bc87	Modified errors into warnings ... No longer false warnings for memories and assertions	2018-06-05 18:03:22 +03:00
Udi Finkelstein	80d9d15f1c	reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files	2018-06-05 18:00:06 +03:00