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emil/codeowners-verilog-ast
Commit Graph
11 Commits
Author SHA1 Message Date
Andrew Zonenberg fc0c7f74dc Added blackbox $__COUNT_ cell model 2017-09-01 06:44:28 -07:00
Andrew Zonenberg 80aaf50302 Refactoring: moved modules still in cells_sim to cells_sim_wip 2017-09-01 06:44:15 -07:00
Andrew Zonenberg b5c15636c5 Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass 2017-08-28 22:18:34 -07:00
Andrew Zonenberg fe3a932cfa Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital 2017-08-14 10:45:39 -07:00
Andrew Zonenberg c53a33143e greenpak4: Can now techmap inferred D latches (without set/reset or output inverter) 2016-12-10 18:46:36 +08:00
Clifford Wolf 5d90a5b905 Added greenpak4_dffinv 2016-08-15 09:33:06 +02:00
Andrew Zonenberg a613f171ae Refactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT cells instead of extract 2016-05-04 15:55:16 -07:00
Andrew Zonenberg dcee3256d5 Added tri-state I/O extraction for GreenPak 2016-05-03 22:53:29 -07:00
Andrew Zonenberg 984561c034 Renamed counters pass to greenpak4_counters 2016-03-30 22:52:01 -07:00
Clifford Wolf 745d56149d Renamed GreenPAK4 cells, improved GP4 DFF mapping 2015-09-18 12:00:37 +02:00
Clifford Wolf c5352f45c3 Added GreenPAK4 skeleton 2015-09-16 09:28:37 +02:00