From fc86bd8e74744a0201c77f6b0c65470795d36d81 Mon Sep 17 00:00:00 2001
From: williamzhu17 <williammzhu@gmail.com>
Date: Sun, 11 May 2025 11:16:50 -0700
Subject: [PATCH] finalized tests

---
 tests/silimate/opt_balance_tree.ys | 115 ++++++++++++++++-------------
 1 file changed, 62 insertions(+), 53 deletions(-)

diff --git a/tests/silimate/opt_balance_tree.ys b/tests/silimate/opt_balance_tree.ys
index 29b16b627..aa42426eb 100644
--- a/tests/silimate/opt_balance_tree.ys
+++ b/tests/silimate/opt_balance_tree.ys
@@ -20,22 +20,18 @@ equiv_opt -assert opt_balance_tree
 design -load postopt
 
 # Checks if inputs to and gates has been rewired
-select -set a_wires i:a %co
-select -set driven_by_a @a_wires %co
+select -set driven_by_a i:a %co %co
 select -set and_a_cell t:$and @driven_by_a %i
 
-select -set b_wires i:b %co
-select -set driven_by_b @b_wires %co
+select -set driven_by_b i:b %co %co
 select -set and_b_cell t:$and @driven_by_b %i
 
 select -assert-none @and_a_cell @and_b_cell %d
 
-select -set c_wires i:c %co
-select -set driven_by_c @c_wires %co
+select -set driven_by_c i:c %co %co
 select -set and_c_cell t:$and @driven_by_c %i
 
-select -set d_wires i:d %co
-select -set driven_by_d @d_wires %co
+select -set driven_by_d i:d %co %co
 select -set and_d_cell t:$and @driven_by_d %i
 
 select -assert-none @and_c_cell @and_d_cell %d
@@ -69,8 +65,7 @@ equiv_opt -assert opt_balance_tree
 design -load postopt
 
 # Checks if y is still wired up to the correct gate
-select -set y_wires o:y %ci
-select -set y_driver @y_wires %ci
+select -set y_driver o:y %ci %ci
 select -set and_y_cell t:$and @y_driver %i
 select @and_y_cell -assert-count 1
 select -set inputs @and_y_cell %ci
@@ -107,6 +102,13 @@ equiv_opt -assert opt_balance_tree
 design -load postopt
 select -assert-count 3 t:$and
 
+# Checks if temp is still wired up to the correct gate
+select -set temp_driver w:temp %ci %ci
+select -set and_cell t:$and @temp_driver %i
+select @and_cell -assert-count 1
+select -set inputs @and_cell %ci
+select -assert-count 1 @inputs i:c %i
+
 design -reset
 log -pop
 
@@ -134,6 +136,42 @@ equiv_opt -assert opt_balance_tree
 design -load postopt
 select -assert-count 3 t:$and
 
+# Checks if x[1] is still wired up to the correct gate
+select -set target_drivers o:x %ci %ci
+select -set target_cells t:$and @target_drivers %i
+select -set inputs @target_cells %ci
+select -assert-count 1 @inputs i:c %i
+
+design -reset
+log -pop
+
+log -header "Fanout going to multiple outputs"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire c,
+  input wire d,
+  output wire [2:0] x,
+  output wire y
+);
+  assign x[0] = a & b;
+  assign x[1] = x[0] & c;
+  assign x[2] = x[1] & d;
+
+  assign y = x[1];
+endmodule
+EOF
+check -assert
+
+# Check equivalence after opt_balance_tree
+equiv_opt -assert opt_balance_tree
+
+design -load postopt
+select -assert-count 3 t:$and
+
 design -reset
 log -pop
 
@@ -164,33 +202,12 @@ equiv_opt -assert opt_balance_tree
 design -load postopt
 select -assert-count 3 t:$and
 
-design -reset
-log -pop
-
-log -header "Fanout going to multiple of the same word"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire a,
-  input wire b,
-  input wire c,
-  input wire d,
-  output wire [3:0] x
-);
-  assign x[0] = a & b;
-  assign x[1] = x[0] & c;
-  assign x[2] = x[1] & d;
-  assign x[3] = x[1];
-endmodule
-EOF
-check -assert
-
-# Check equivalence after opt_balance_tree
-equiv_opt -assert opt_balance_tree
-
-design -load postopt
-select -assert-count 3 t:$and
+# Checks if y is still wired up to the correct gate
+select -set y_wires o:y %ci
+select -set y_driver @y_wires %ci %ci
+select -set and_y_cell t:$and @y_driver %i
+select -set inputs @and_y_cell %ci
+select -assert-count 1 @inputs i:c %i
 
 design -reset
 log -pop
@@ -222,45 +239,37 @@ design -load postopt
 # Checks if inputs to and gates has been rewired
 
 # a and b
-select -set a_wires i:a %co
-select -set driven_by_a @a_wires %co
+select -set driven_by_a i:a %co %co
 select -set and_a_cell t:$and @driven_by_a %i
 
-select -set b_wires i:b %co
-select -set driven_by_b @b_wires %co
+select -set driven_by_b i:b %co %co
 select -set and_b_cell t:$and @driven_by_b %i
 
 select -assert-none @and_a_cell @and_b_cell %d
 
 # c and d
-select -set c_wires i:c %co
-select -set driven_by_c @c_wires %co
+select -set driven_by_c i:c %co %co
 select -set and_c_cell t:$and @driven_by_c %i
 
-select -set d_wires i:d %co
-select -set driven_by_d @d_wires %co
+select -set driven_by_d i:d %co %co
 select -set and_d_cell t:$and @driven_by_d %i
 
 select -assert-none @and_c_cell @and_d_cell %d
 
 # e and f
-select -set e_wires i:e %co
-select -set driven_by_e @e_wires %co
+select -set driven_by_e i:e %co %co
 select -set and_e_cell t:$and @driven_by_e %i
 
-select -set f_wires i:f %co
-select -set driven_by_f @f_wires %co
+select -set driven_by_f i:f %co %co
 select -set and_f_cell t:$and @driven_by_f %i
 
 select -assert-none @and_e_cell @and_f_cell %d
 
 # g and h
-select -set g_wires i:g %co
-select -set driven_by_g @g_wires %co
+select -set driven_by_g i:g %co %co
 select -set and_g_cell t:$and @driven_by_g %i
 
-select -set h_wires i:h %co
-select -set driven_by_h @h_wires %co
+select -set driven_by_h i:h %co %co
 select -set and_h_cell t:$and @driven_by_h %i
 
 select -assert-none @and_g_cell @and_h_cell %d