From fc61433faa24f1fd6b1fa10a1b98be3a010e2191 Mon Sep 17 00:00:00 2001
From: AdvaySingh1 <advay@umich.edu>
Date: Fri, 30 Jan 2026 13:11:36 -0800
Subject: [PATCH] Reducing verbosity for cell printing

---
 passes/techmap/abc.cc | 1 -
 1 file changed, 1 deletion(-)

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 9af012a44..1742cdd9d 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1490,7 +1490,6 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict<SigSpec, std::string> &
 	for (auto c : mapped_mod->cells())
 	{
 		// SILIMATE: set output port to either Y or Q depending on the cell's ports and apply src attribute to the driver cell
-		log("Processing cell %s\n", c->name.c_str());
 		pool<string> src_pool;
 		if (c->hasPort(ID::Y) || c->hasPort(ID::Q)) {
 			Wire *out_wire = c->getPort((c->hasPort(ID::Y)) ? ID::Y : ID::Q).as_wire();