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rtlil: remove dead verilog bindings

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This commit is contained in:
Emil J. Tywoniak
2026-08-31 22:13:01 +02:00
parent c30457480f
commit fbd7c249ec
28 changed files with 5 additions and 494 deletions
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kernel/CMakeLists.txt
-3
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@@ -15,8 +15,6 @@ foreach (library simlib simcells)
endforeach()
yosys_core(kernel
binding.cc
binding.h
bitpattern.h
calc.cc
cellaigs.cc
@@ -115,7 +113,6 @@ yosys_core(kernel
DATA_DIR
include/kernel
DATA_FILES
binding.h
bitpattern.h
cellaigs.h
celledges.h
kernel/binding.cc
-29
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@@ -1,29 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "binding.h"
YOSYS_NAMESPACE_BEGIN
RTLIL::Binding::Binding(RTLIL::IdString target_type,
RTLIL::IdString target_name)
: target_type(target_type), target_name(target_name)
{}
YOSYS_NAMESPACE_END
kernel/binding.h
-60
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@@ -1,60 +0,0 @@
/* -*- c++ -*-
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#ifndef BINDING_H
#define BINDING_H
#include "kernel/rtlil.h"
YOSYS_NAMESPACE_BEGIN
struct RTLIL::Binding
{
// Represents a bind construct.
//
// The target of the binding is represented by target_type and
// target_name (see comments above the fields).
Binding(RTLIL::IdString target_type,
RTLIL::IdString target_name);
virtual ~Binding() {}
// Return a string describing the binding
virtual std::string describe() const = 0;
protected:
// May be empty. If not, it's the name of the module or interface to
// bind to.
RTLIL::IdString target_type;
// If target_type is nonempty (the usual case), this is a hierarchical
// reference to the bind target. If target_type is empty, we have to
// wait until the hierarchy pass to figure out whether this was the name
// of a module/interface type or an instance.
RTLIL::IdString target_name;
// An attribute name which contains an ID that's unique across binding
// instances (used to ensure we don't apply a binding twice to a module)
RTLIL::IdString attr_name;
};
YOSYS_NAMESPACE_END
#endif
kernel/rtlil.cc
-17
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@@ -20,7 +20,6 @@
#include "kernel/yosys.h"
#include "kernel/macc.h"
#include "kernel/newcelltypes.h"
#include "kernel/binding.h"
#include "kernel/sigtools.h"
#include "kernel/threading.h"
#include "frontends/verilog/verilog_frontend.h"
@@ -1185,8 +1184,6 @@ RTLIL::Design::~Design()
{
for (auto &pr : modules_)
delete pr.second;
for (auto n : bindings_)
delete n;
RTLIL::Design::get_all_designs()->erase(hashidx_);
}
@@ -1226,12 +1223,6 @@ RTLIL::Module *RTLIL::Design::top_module() const
return module_count == 1 ? module : nullptr;
}
void RTLIL::Design::add(RTLIL::Binding *binding)
{
log_assert(binding != nullptr);
bindings_.push_back(binding);
}
RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
{
if (modules_.count(name) != 0)
@@ -1531,8 +1522,6 @@ RTLIL::Module::~Module()
delete pr.second;
for (auto &pr : processes)
delete pr.second;
for (auto binding : bindings_)
delete binding;
#ifdef YOSYS_ENABLE_PYTHON
RTLIL::Module::get_all_modules()->erase(hashidx_);
#endif
@@ -2892,12 +2881,6 @@ void RTLIL::Module::add(RTLIL::Process *process)
process->module = this;
}
void RTLIL::Module::add(RTLIL::Binding *binding)
{
log_assert(binding != nullptr);
bindings_.push_back(binding);
}
void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
{
log_assert(refcount_wires_ == 0);
kernel/rtlil.h
-6
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@@ -122,7 +122,6 @@ namespace RTLIL
struct MemWriteAction;
struct SyncRule;
struct Process;
struct Binding;
struct IdString;
struct OwningIdString;
@@ -1902,7 +1901,6 @@ struct RTLIL::Design
int refcount_modules_;
dict<RTLIL::IdString, RTLIL::Module*> modules_;
std::vector<RTLIL::Binding*> bindings_;
std::vector<std::unique_ptr<AST::AstNode>> verilog_packages, verilog_globals;
std::unique_ptr<define_map_t> verilog_defines;
@@ -1924,7 +1922,6 @@ struct RTLIL::Design
}
void add(RTLIL::Module *module);
void add(RTLIL::Binding *binding);
RTLIL::Module *addModule(RTLIL::IdString name);
void remove(RTLIL::Module *module);
@@ -2078,7 +2075,6 @@ public:
dict<RTLIL::IdString, RTLIL::Cell*> cells_;
std::vector<RTLIL::SigSig> connections_;
std::vector<RTLIL::Binding*> bindings_;
idict<RTLIL::IdString> avail_parameters;
dict<RTLIL::IdString, RTLIL::Const> parameter_default_values;
@@ -2166,8 +2162,6 @@ public:
int cells_size() const { return cells_.size(); }
RTLIL::Cell* cell_at(int index) const { return cells_.element(index)->second; }
void add(RTLIL::Binding *binding);
// Removing wires is expensive. If you have to remove wires, remove them all at once.
void remove(const pool<RTLIL::Wire*> &wires);
void remove(RTLIL::Cell *cell);