mirror of https://github.com/YosysHQ/yosys.git
Make opt_compact_prefix match more
This commit is contained in:
Akash Levy
parent
b60d2daa41
commit
faea2d904a
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@ -19,6 +19,7 @@
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/consteval.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -44,6 +45,7 @@ struct OptCompactPrefixWorker
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int forward_rewrites = 0;
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int reverse_rewrites = 0;
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int modulo_rewrites = 0;
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int old_cells_removed = 0;
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int new_cells_emitted = 0;
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@ -329,6 +331,25 @@ struct OptCompactPrefixWorker
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return SigBit(out);
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}
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SigBit emit_bmux(SigSpec table, SigSpec sel)
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{
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Cell *cell = ref_cell;
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log_assert(cell != nullptr);
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Wire *out = module->addWire(NEW_ID2_SUFFIX("compact_div"), 1);
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module->addBmux(NEW_ID2_SUFFIX("compact_bmux"), table, sel, out);
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new_cells_emitted++;
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return SigBit(out);
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}
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static Const const_u64(uint64_t value, int width)
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{
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vector<State> bits(width, State::S0);
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for (int i = 0; i < width && i < 64; i++)
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if ((value >> i) & 1ULL)
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bits[i] = State::S1;
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return Const(bits);
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}
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void remove_old_cells(const vector<Cell *> &old_cells)
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{
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for (auto cell : old_cells) {
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@ -468,13 +489,200 @@ struct OptCompactPrefixWorker
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return true;
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}
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// Reference function for the modulo-n decimation loop: scanning the enable
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// vector from one end, mark every n-th enabled bit. Equivalent closed form:
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// mask[I] = en[I] && n>0 && (inclusive_popcount(I) % n == 0)
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// where the popcount runs from the scan's leading end down to (incl.) I.
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uint64_t expected_modulo_mask(uint64_t en, uint64_t n, int width, bool msb_first)
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{
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if (n == 0)
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return 0;
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uint64_t mask = 0;
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for (int i = 0; i < width; i++) {
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if (!((en >> i) & 1ULL))
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continue;
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uint64_t v = 0;
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if (msb_first)
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for (int k = i; k < width; k++)
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v += (en >> k) & 1ULL;
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else
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for (int k = 0; k <= i; k++)
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v += (en >> k) & 1ULL;
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if (v % n == 0)
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mask |= (1ULL << i);
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}
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return mask;
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}
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// Confirm the combinational function from (en, n) to mask matches the modulo
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// decimation reference for the given scan direction, using ConstEval over a
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// structured + pseudo-random vector set (cf. opt_argmax's fingerprint).
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bool fingerprint_modulo(Wire *en, Wire *n, Wire *mask, int width, bool msb_first)
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{
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if (width <= 0 || width > 62)
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return false;
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ConstEval ce(module);
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SigSpec en_sig = sigmap(SigSpec(en));
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SigSpec n_sig = sigmap(SigSpec(n));
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SigSpec mask_sig = sigmap(SigSpec(mask));
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int nw = GetSize(n);
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vector<uint64_t> nvals;
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uint64_t nmax = (nw >= 64) ? ~0ULL : ((1ULL << nw) - 1);
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for (uint64_t v = 0; v <= (uint64_t)width + 1 && v <= nmax; v++)
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nvals.push_back(v);
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if (nmax > (uint64_t)width + 1)
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nvals.push_back(nmax);
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uint64_t full = (width >= 64) ? ~0ULL : ((1ULL << width) - 1);
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vector<uint64_t> envals;
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envals.push_back(0);
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envals.push_back(full);
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envals.push_back(full & 0x5555555555555555ULL);
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envals.push_back(full & 0xAAAAAAAAAAAAAAAAULL);
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for (int i = 0; i < width; i++)
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envals.push_back(1ULL << i);
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uint64_t lfsr = 0x1234567089abcdefULL;
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for (int r = 0; r < 64; r++) {
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lfsr ^= lfsr << 13;
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lfsr ^= lfsr >> 7;
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lfsr ^= lfsr << 17;
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envals.push_back(lfsr & full);
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}
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for (uint64_t nv : nvals)
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for (uint64_t ev : envals) {
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ce.push();
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ce.set(en_sig, const_u64(ev, width));
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ce.set(n_sig, const_u64(nv, nw));
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SigSpec out = mask_sig;
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SigSpec undef;
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bool ok = ce.eval(out, undef);
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ce.pop();
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if (!ok || !out.is_fully_const())
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return false;
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Const cv = out.as_const();
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uint64_t actual = 0;
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for (int i = 0; i < width && i < 64; i++)
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if (cv[i] == State::S1)
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actual |= (1ULL << i);
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if (actual != expected_modulo_mask(ev, nv, width, msb_first))
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return false;
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}
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return true;
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}
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bool rewrite_modulo_decimation()
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{
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vector<Wire *> inputs = input_ports();
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vector<Wire *> outputs = output_ports();
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if (GetSize(inputs) != 2 || GetSize(outputs) != 1)
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return false;
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if (GetSize(module->ports) != 3)
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return false;
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Wire *mask = outputs[0];
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int width = GetSize(mask);
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if (width < 4 || width > max_width)
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return false;
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// en matches the mask width; n (the modulus) is a distinct, narrower bus.
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// Requiring different widths also disambiguates from the reverse suffix
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// read form, whose two inputs share the mask width.
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Wire *en = nullptr, *n = nullptr;
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for (auto in : inputs) {
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if (GetSize(in) == width && en == nullptr)
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en = in;
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else
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n = in;
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}
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if (en == nullptr || n == nullptr || en == n || GetSize(n) == width)
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return false;
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bool msb_first;
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if (fingerprint_modulo(en, n, mask, width, true))
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msb_first = true;
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else if (fingerprint_modulo(en, n, mask, width, false))
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msb_first = false;
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else
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return false;
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vector<Cell *> old_cells(module->cells().begin(), module->cells().end());
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if (old_cells.empty())
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return false;
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ref_cell = old_cells.front();
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int cnt_width = ceil_log2_int(width + 1);
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int table_size = 1 << cnt_width;
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int cmp_width = std::max(GetSize(n), cnt_width);
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auto en_bit = [&](int i) { return sigmap(SigBit(en, i)); };
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// 1) Inclusive prefix popcount as a naive linear $add cascade. Each
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// running sum is consumed below, so the downstream opt_parallel_prefix
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// pass rebuilds the cascade into a shared log-depth prefix network.
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vector<SigSpec> popcount(width);
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Cell *cell = ref_cell;
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int start = msb_first ? width - 1 : 0;
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int step = msb_first ? -1 : 1;
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int last = msb_first ? 0 : width - 1;
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SigSpec acc = SigSpec(en_bit(start));
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popcount[start] = zext(acc, cnt_width);
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for (int i = start + step; i != last + step; i += step) {
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Wire *sum = module->addWire(NEW_ID2_SUFFIX("compact_pop"), cnt_width);
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module->addAdd(NEW_ID2_SUFFIX("compact_pop_add"), acc, SigSpec(en_bit(i)), sum);
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new_cells_emitted++;
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acc = SigSpec(sum);
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popcount[i] = SigSpec(sum);
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}
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// 2) Decode the modulus once: eq_d = (n == d) for d in [1..width].
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vector<SigBit> eqd(width + 1, State::S0);
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for (int d = 1; d <= width; d++)
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eqd[d] = emit_eq(SigSpec(n), d, cmp_width);
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// 3) Divisibility per popcount value: div_k = OR_{d | k} eq_d. n>0 and
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// n>width fall out for free (no divisor in range matches).
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vector<SigBit> divisible(table_size, State::S0);
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divisible[0] = State::S1; // gated away by en[]; defined to size the table
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for (int k = 1; k <= width; k++) {
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SigSpec terms;
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for (int d = 1; d <= k; d++)
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if (k % d == 0)
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terms.append(SigSpec(eqd[d]));
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divisible[k] = emit_reduce_or(terms);
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}
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// 4) Shared divisibility table; select per bit by its popcount value.
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SigSpec table;
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for (int k = 0; k < table_size; k++)
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table.append(SigSpec(divisible[k]));
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SigSpec out_bits;
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for (int i = 0; i < width; i++) {
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SigBit sel_divisible = emit_bmux(table, popcount[i]);
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out_bits.append(emit_and(en_bit(i), sel_divisible));
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}
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module->connect(SigSpec(mask), out_bits);
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remove_old_cells(old_cells);
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log(" Modulo decimation: en=%s, n=%s -> %s, width=%d, %s scan.\n",
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log_id(en->name), log_id(n->name), log_id(mask->name), width,
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msb_first ? "MSB-first" : "LSB-first");
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modulo_rewrites++;
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return true;
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}
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void run()
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{
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if (module->has_processes_warn())
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return;
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if (rewrite_forward_dense_pack())
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return;
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rewrite_reverse_suffix_read();
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if (rewrite_reverse_suffix_read())
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return;
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rewrite_modulo_decimation();
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}
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};
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@ -492,9 +700,16 @@ struct OptCompactPrefixPass : public Pass
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log("lowering of SystemVerilog loops and replace their long loop-carried\n");
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log("index/update cones with balanced prefix-count and routing logic.\n");
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log("\n");
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log("Currently this pass handles the dense bit-pack and reverse suffix-read\n");
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log("forms used by the qor_spi_ra_add_chain and qor_spi_ra_sub_chain\n");
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log("regressions. Non-matching modules are left unchanged.\n");
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log("Currently this pass handles the dense bit-pack, reverse suffix-read,\n");
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log("and modulo-n decimation forms used by the qor_spi_ra_add_chain,\n");
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log("qor_spi_ra_sub_chain, and qor_spi_ra_add_chain2 regressions.\n");
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log("Non-matching modules are left unchanged.\n");
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log("\n");
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log("The modulo decimation form (mark every n-th enabled bit while scanning\n");
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log("the enable vector) is lowered to a prefix-popcount plus divisor-decode\n");
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log("divisibility check. The popcount is emitted as a plain linear $add\n");
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log("cascade so a subsequent opt_parallel_prefix pass can rebuild it into a\n");
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log("shared log-depth network.\n");
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log("\n");
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log(" -max_width <n>\n");
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log(" Maximum compaction width to rewrite. Default: 64.\n");
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@ -518,6 +733,7 @@ struct OptCompactPrefixPass : public Pass
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int total_forward = 0;
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int total_reverse = 0;
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int total_modulo = 0;
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int total_removed = 0;
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int total_emitted = 0;
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@ -526,15 +742,16 @@ struct OptCompactPrefixPass : public Pass
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worker.run();
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total_forward += worker.forward_rewrites;
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total_reverse += worker.reverse_rewrites;
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total_modulo += worker.modulo_rewrites;
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total_removed += worker.old_cells_removed;
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total_emitted += worker.new_cells_emitted;
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}
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log("Rewrote %d forward pack(s), %d reverse suffix read(s); "
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log("Rewrote %d forward pack(s), %d reverse suffix read(s), %d modulo decimation(s); "
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"removed %d old cell(s), emitted %d new cell(s).\n",
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total_forward, total_reverse, total_removed, total_emitted);
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total_forward, total_reverse, total_modulo, total_removed, total_emitted);
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if (total_forward || total_reverse)
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if (total_forward || total_reverse || total_modulo)
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Yosys::run_pass("clean -purge");
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}
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} OptCompactPrefixPass;
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@ -350,3 +350,117 @@ select -assert-none opt_compact_prefix_multi_match/t:$mux
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select -assert-count 1 opt_compact_prefix_multi_keep/t:$mux
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design -reset
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log -pop
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log -header "Modulo decimation self-equivalence (MSB-first)"
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log -push
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design -reset
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verific -cfg veri_optimize_wide_selector 1
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verific -cfg db_infer_wide_muxes_post_elaboration 0
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read -sv opt_compact_prefix_mod.sv
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verific -import opt_compact_prefix_mod8
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proc; opt_clean
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rename opt_compact_prefix_mod8 gold
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read -sv opt_compact_prefix_mod.sv
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verific -import opt_compact_prefix_mod8
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proc; opt_clean
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opt_compact_prefix
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opt_clean
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bmuxmap
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rename opt_compact_prefix_mod8 gate
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miter -equiv -flatten -make_assert gold gate miter
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hierarchy -top miter
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proc; opt; memory; opt
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sat -prove-asserts -verify
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design -reset
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log -pop
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log -header "Modulo decimation self-equivalence (LSB-first)"
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log -push
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design -reset
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verific -cfg veri_optimize_wide_selector 1
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verific -cfg db_infer_wide_muxes_post_elaboration 0
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read -sv opt_compact_prefix_mod.sv
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verific -import opt_compact_prefix_mod_lsb8
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proc; opt_clean
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rename opt_compact_prefix_mod_lsb8 gold
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read -sv opt_compact_prefix_mod.sv
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verific -import opt_compact_prefix_mod_lsb8
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proc; opt_clean
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opt_compact_prefix
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opt_clean
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bmuxmap
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rename opt_compact_prefix_mod_lsb8 gate
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miter -equiv -flatten -make_assert gold gate miter
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hierarchy -top miter
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proc; opt; memory; opt
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sat -prove-asserts -verify
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design -reset
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log -pop
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log -header "Modulo decimation structural rewrite"
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log -push
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design -reset
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verific -cfg veri_optimize_wide_selector 1
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verific -cfg db_infer_wide_muxes_post_elaboration 0
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read -sv opt_compact_prefix_mod.sv
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verific -import opt_compact_prefix_mod16
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proc; opt_clean
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opt_compact_prefix
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opt_clean
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select -assert-none t:$mux
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select -assert-none t:$sub
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select -assert-min 1 t:$add
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select -assert-min 1 t:$eq
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select -assert-min 1 t:$bmux
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design -reset
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log -pop
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log -header "Modulo decimation: opt_parallel_prefix collapses the popcount cascade"
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log -push
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design -reset
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verific -cfg veri_optimize_wide_selector 1
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verific -cfg db_infer_wide_muxes_post_elaboration 0
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read -sv opt_compact_prefix_mod.sv
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verific -import opt_compact_prefix_mod16
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proc; opt_clean
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opt_compact_prefix
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opt_clean
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opt_parallel_prefix -arith
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opt_clean
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select -assert-none t:$mux
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select -assert-none t:$sub
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select -assert-min 1 t:$add
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design -reset
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log -pop
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log -header "Negative: modulo off-by-one near miss unchanged"
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log -push
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design -reset
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verific -cfg veri_optimize_wide_selector 1
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verific -cfg db_infer_wide_muxes_post_elaboration 0
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read -sv opt_compact_prefix_mod.sv
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verific -import opt_compact_prefix_mod_offbyone
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proc; opt_clean
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opt_compact_prefix
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select -assert-none w:*compact*
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design -reset
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log -pop
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log -header "Max width: modulo decimation left unchanged"
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log -push
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design -reset
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verific -cfg veri_optimize_wide_selector 1
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verific -cfg db_infer_wide_muxes_post_elaboration 0
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read -sv opt_compact_prefix_mod.sv
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verific -import opt_compact_prefix_mod16
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proc; opt_clean
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select -assert-min 1 t:$mux
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opt_compact_prefix -max_width 8
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select -assert-min 1 t:$mux
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select -assert-none w:*compact*
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design -reset
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log -pop
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@ -0,0 +1,86 @@
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// Modulo-n decimation loops: scanning the enable vector, mark every n-th
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// enabled bit. Exercised by opt_compact_prefix's modulo decimation rewrite
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// (cf. the qor_spi_ra_add_chain2 regression).
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module opt_compact_prefix_mod8 (
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input logic [7:0] en,
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input logic [3:0] n,
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output logic [7:0] mask
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);
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always_comb begin
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mask = '0;
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for (int I = 7, cnt = 0; I >= 0; I--) begin
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if (en[I] && (n > 0)) begin
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if (cnt == (n - 1)) begin
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mask[I] = 1'b1;
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cnt = 0;
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end else begin
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cnt++;
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end
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end
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end
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end
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endmodule
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module opt_compact_prefix_mod16 (
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input logic [15:0] en,
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input logic [4:0] n,
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output logic [15:0] mask
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||||
);
|
||||
always_comb begin
|
||||
mask = '0;
|
||||
for (int I = 15, cnt = 0; I >= 0; I--) begin
|
||||
if (en[I] && (n > 0)) begin
|
||||
if (cnt == (n - 1)) begin
|
||||
mask[I] = 1'b1;
|
||||
cnt = 0;
|
||||
end else begin
|
||||
cnt++;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
// Same function, but scanned LSB-first (exercises the mirrored direction).
|
||||
module opt_compact_prefix_mod_lsb8 (
|
||||
input logic [7:0] en,
|
||||
input logic [3:0] n,
|
||||
output logic [7:0] mask
|
||||
);
|
||||
always_comb begin
|
||||
mask = '0;
|
||||
for (int I = 0, cnt = 0; I < 8; I++) begin
|
||||
if (en[I] && (n > 0)) begin
|
||||
if (cnt == (n - 1)) begin
|
||||
mask[I] = 1'b1;
|
||||
cnt = 0;
|
||||
end else begin
|
||||
cnt++;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
// Negative near-miss: marks every (n+1)-th enabled bit (reset on cnt == n),
|
||||
// a different function that must NOT be rewritten.
|
||||
module opt_compact_prefix_mod_offbyone (
|
||||
input logic [7:0] en,
|
||||
input logic [3:0] n,
|
||||
output logic [7:0] mask
|
||||
);
|
||||
always_comb begin
|
||||
mask = '0;
|
||||
for (int I = 7, cnt = 0; I >= 0; I--) begin
|
||||
if (en[I] && (n > 0)) begin
|
||||
if (cnt == n) begin
|
||||
mask[I] = 1'b1;
|
||||
cnt = 0;
|
||||
end else begin
|
||||
cnt++;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
Loading…
Reference in New Issue