mirror of https://github.com/YosysHQ/yosys.git
87 lines
2.0 KiB
Systemverilog
87 lines
2.0 KiB
Systemverilog
// Modulo-n decimation loops: scanning the enable vector, mark every n-th
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// enabled bit. Exercised by opt_compact_prefix's modulo decimation rewrite
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// (cf. the qor_spi_ra_add_chain2 regression).
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module opt_compact_prefix_mod8 (
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input logic [7:0] en,
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input logic [3:0] n,
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output logic [7:0] mask
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);
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always_comb begin
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mask = '0;
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for (int I = 7, cnt = 0; I >= 0; I--) begin
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if (en[I] && (n > 0)) begin
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if (cnt == (n - 1)) begin
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mask[I] = 1'b1;
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cnt = 0;
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end else begin
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cnt++;
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end
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end
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end
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end
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endmodule
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module opt_compact_prefix_mod16 (
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input logic [15:0] en,
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input logic [4:0] n,
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output logic [15:0] mask
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);
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always_comb begin
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mask = '0;
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for (int I = 15, cnt = 0; I >= 0; I--) begin
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if (en[I] && (n > 0)) begin
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if (cnt == (n - 1)) begin
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mask[I] = 1'b1;
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cnt = 0;
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end else begin
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cnt++;
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end
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end
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end
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end
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endmodule
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// Same function, but scanned LSB-first (exercises the mirrored direction).
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module opt_compact_prefix_mod_lsb8 (
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input logic [7:0] en,
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input logic [3:0] n,
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output logic [7:0] mask
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);
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always_comb begin
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mask = '0;
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for (int I = 0, cnt = 0; I < 8; I++) begin
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if (en[I] && (n > 0)) begin
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if (cnt == (n - 1)) begin
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mask[I] = 1'b1;
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cnt = 0;
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end else begin
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cnt++;
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end
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end
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end
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end
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endmodule
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// Negative near-miss: marks every (n+1)-th enabled bit (reset on cnt == n),
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// a different function that must NOT be rewritten.
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module opt_compact_prefix_mod_offbyone (
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input logic [7:0] en,
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input logic [3:0] n,
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output logic [7:0] mask
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);
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always_comb begin
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mask = '0;
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for (int I = 7, cnt = 0; I >= 0; I--) begin
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if (en[I] && (n > 0)) begin
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if (cnt == n) begin
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mask[I] = 1'b1;
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cnt = 0;
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end else begin
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cnt++;
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end
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end
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end
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end
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endmodule
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